Editing Static random-access memory (section)

===By feature===
* Zero bus turnaround (ZBT){{snd}} the turnaround is the number of clock cycles it takes to change access to SRAM from ''write'' to ''read'' and vice versa. The turnaround for ZBT SRAMs or the latency between read and write cycle is zero.
* syncBurst (syncBurst SRAM or synchronous-burst SRAM){{snd}} features synchronous burst write access to SRAM to increase write operation to SRAM.
* DDR SRAM{{snd}} synchronous, single read/write port, double data rate I/O.
* [[Quad Data Rate SRAM]]{{snd}} synchronous, separate read and write ports, quadruple data rate I/O.