Editing Verilog (section)

==Race conditions==
The order of execution is not always guaranteed within Verilog. This can best be illustrated by a classic example. Consider the code snippet below:
<syntaxhighlight lang="verilog">
initial
  a = 0;

initial
  b = a;

initial
  begin
    #1;
    $display("Value a=%d Value of b=%d",a,b);
  end
</syntaxhighlight>

Depending on the order of execution of the initial blocks, it could be zero and zero, or alternately zero and some other arbitrary uninitialized value.  The <code>$display</code> statement will always execute after both assignment blocks have completed, due to the #1 delay.