Editing Direct memory access (section)

=== Cell ===
{{main|Cell (microprocessor)}}

As an example usage of DMA in a [[multiprocessor-system-on-chip]], IBM/Sony/Toshiba's [[Cell processor]] incorporates a DMA engine for each of its 9 processing elements including one Power processor element (PPE) and eight synergistic processor elements (SPEs). Since the SPE's load/store instructions can read/write only its own local memory, an SPE entirely depends on DMAs to transfer data to and from the main memory and local memories of other SPEs. Thus the DMA acts as a primary means of data transfer among cores inside this [[CPU]] (in contrast to cache-coherent CMP architectures such as Intel's cancelled [[GPGPU|general-purpose GPU]], [[Larrabee (microarchitecture)|Larrabee]]).

DMA in Cell is fully [[#Cache coherency|cache coherent]] (note however local stores of SPEs operated upon by DMA do not act as globally coherent cache in the [[CPU cache|standard sense]]). In both read ("get") and write ("put"), a DMA command can transfer either a single block area of size up to 16 KB, or a list of 2 to 2048 such blocks. The DMA command is issued by specifying a pair of a local address and a remote address: for example when a SPE program issues a put DMA command, it specifies an address of its own local memory as the source and a virtual memory address (pointing to either the main memory or the local memory of another SPE) as the target, together with a block size. According to an experiment, an effective peak performance of DMA in Cell (3&nbsp;GHz, under uniform traffic) reaches 200 GB per second.<ref name="petrini-cell">{{cite journal |first=Michael |last=Kistler |title=Cell Multiprocessor Communication Network: Built for Speed |journal=[[IEEE Micro]] |date=May 2006|volume=26 |issue=3 |pages=10–23 |doi=10.1109/MM.2006.49 |s2cid=7735690 |url=http://portal.acm.org/citation.cfm?id=1158825.1159067 |url-access=subscription }}</ref>