Editing List of interface bit rates (section)

====Main buses====
{|class="wikitable sortable"
|-
! Technology !! colspan=2 | Rate !! Year
|-
| [[I²C]] || align=right | '''{{val|3.4|u=Mbit/s}}''' || align=right | {{val|425|u=kB/s}} || 1992 (standardized)
|-
| [[Apple II]] (incl. [[Apple IIGS]]) 8-bit/1&nbsp;MHz || align=right | '''{{val|8|u=Mbit/s}}''' || align=right | {{val|1|u=MB/s}}<ref>[https://www.mac-history.net/computer-history/2008-05-25/apple-i-and-apple-ii Mac History]</ref><ref>[http://www.vectronicsappleworld.com/profiles/83.html VAW: Apple IIgs Specs] {{webarchive|url=https://web.archive.org/web/20110110075801/http://www.vectronicsappleworld.com/profiles/83.html |date=2011-01-10}}</ref> || 1977
|-
| [[SS-50 Bus]] 8-bit/1&nbsp;MHz || align=right | '''{{val|8|u=Mbit/s}}''' || align=right | {{val|1|u=MB/s}} || 1975
|-
| [[Unibus]] 16-bit/async || align=right | '''{{val|12|u=Mbit/s}}''' || align=right | {{val|1.5|u=MB/s}} || 1969
|-
| [[STD-80]] 8-bit/8&nbsp;MHz || align=right | '''{{val|16|u=Mbit/s}}''' || align=right | {{val|2|u=MB/s}} ||
|-
| [[Q-bus]] 16-bit/async || align=right | '''{{val|24|u=Mbit/s}}''' || align=right | {{val|3|u=MB/s}} || 1975
|-
| [[Industry Standard Architecture|ISA]] 8-Bit/4.77&nbsp;MHz || align=right | 0 W/S: every 4 clocks 8 bits<br />1 W/S: every 5 clocks 8 bits || align=right | 0 W/S: every 4 clocks 1 byte<br />1 W/S: every 5 clocks 1 byte || 1981 (created)
|-
| STD-80 16-bit/8&nbsp;MHz || align=right | '''{{val|32|u=Mbit/s}}''' || align=right | {{val|4|u=MB/s}} ||
|-
|[[I3C (bus)|I3C (HDR mode)]]<ref>{{cite web |url=http://eecatalog.com/sensors/2017/07/05/after-35-years-of-i2c-i3c-improves-capability-and-performance/ |title=After 35 years of I2C, I3C Improves Capability and Performance {{!}} Sensors and MEMS|website=eecatalog.com|access-date=2019-06-26}}</ref>|| align="right" |'''{{val|33.3|u=Mbit/s}}''' || align=right | {{val|4.16|u=MB/s}} || 2017
|-
| [[Zorro II]] 16-bit/7.14&nbsp;MHz<ref>The [[Zorro II]] bus use 4 clocks per 16-Bit of data transferred. See the [http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf Zorro III technical specification] {{Webarchive|url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf |date=2012-07-16}} for more information.</ref> || align=right | '''{{val|42.4|u=Mbit/s}}''' || align=right | {{val|5.3|u=MB/s}} || 1986
|-
| [[Industry Standard Architecture|ISA]] 16-Bit/8.33&nbsp;MHz || align=right | '''{{val|66.64|u=Mbit/s}}''' || align=right | {{val|8.33|u=MB/s}} || 1984 (created)
|-
| [[Europe Card Bus]] 8-Bit/10&nbsp;MHz || align=right | '''{{val|66.7|u=Mbit/s}}''' || align=right | {{val|8.33|u=MB/s}} || 1977 (created)
|-
| [[S-100 bus]] 8-bit/10&nbsp;MHz || align=right | '''{{val|80|u=Mbit/s}}''' || align=right | {{val|10|u=MB/s}} || 1976 (published)
|-
| [[Serial Peripheral Interface]] (Up to 100&nbsp;MHz) || align=right | '''{{val|100|u=Mbit/s}}''' || align=right | {{val|12.5|u=MB/s}} || 1989
|-
| [[Low Pin Count]] || align=right | '''{{val|125|u=Mbit/s}}''' || align=right | {{val|15.63|u=MB/s}} {{ref label|lpc|x|x}}|| 2002
|-
| [[STEbus]] 8-Bit/16&nbsp;MHz || align=right | '''{{val|128|u=Mbit/s}}''' || align=right | {{val|16|u=MB/s}} || 1987 (standardized)
|-
| [[C-Bus (PC98)|C-Bus]] 16-bit/10&nbsp;MHz || align=right | '''{{val|160|u=Mbit/s}}''' || align=right | {{val|20|u=MB/s}}<ref>[[:ja:Cバス|Japan wikipedia article]], Bus used in early NEC PC-9800 series and compatible systems</ref> || 1982
|-
| [[HP Precision Bus]] || align=right | '''{{val|184|u=Mbit/s}}''' || align=right | {{val|23|u=MB/s}} ||
|-
| [[STD Bus#STD-32|STD-32]] 32-bit/8&nbsp;MHz || align=right | '''{{val|256|u=Mbit/s}}''' || align=right | {{val|32|u=MB/s}}<ref>[http://www.controlled.com/std32mg/std32.pdf STD 32 Bus Specification and Designer's Guide]</ref> ||
|-
| [[New Extend Standard Architecture|NESA]] 32-bit/8&nbsp;MHz || align=right | '''{{val|256|u=Mbit/s}}''' || align=right | {{val|32|u=MB/s}}<ref>[[:ja:New Extend Standard Architecture|Japan wikipedia article]], Bus used in later NEC PC-9800 series and compatible systems</ref> ||
|-
| [[Extended Industry Standard Architecture|EISA]] 32-bit/8.33&nbsp;MHz || align=right | '''{{val|266.56|u=Mbit/s}}''' || align=right | {{val|33.32|u=MB/s}} || 1988
|-
| [[VMEbus|VME64]] 32-64bit || align=right | '''{{val|400|u=Mbit/s}}''' || align=right | {{val|40|u=MB/s}} || 1981
|-
| [[Micro Channel architecture|MCA]] 32bit/10&nbsp;MHz || align=right | '''{{val|400|u=Mbit/s}}''' || align=right | {{val|40|u=MB/s}} || 1987
|-
| [[NuBus]] 10&nbsp;MHz || align=right | '''{{val|400|u=Mbit/s}}''' || align=right | {{val|40|u=MB/s}} || 1987 (standardized)
|-
| DEC [[TURBOchannel]] 32-bit/12.5&nbsp;MHz || align=right | '''{{val|400|u=Mbit/s}}''' || align=right | {{val|50|u=MB/s}} ||
|-
| NuBus90 20&nbsp;MHz || align=right | '''{{val|800|u=Mbit/s}}''' || align=right | {{val|80|u=MB/s}} || 1991
|-
| [[Micro Channel architecture|MCA]] 32bit/20&nbsp;MHz || align=right | '''{{val|800|u=Mbit/s}}''' || align=right | {{val|80|u=MB/s}}<ref>[https://www.ibm.com/common/ssi/rep_ca/9/877/ENUSZG92-0339/index.html RISC System/6000 POWERstation/POWERserver 580]</ref> || 1992
|-
| [[APbus]] 32-bit/25(?)&nbsp;MHz || align=right | '''{{val|800|u=Mbit/s}}''' || align=right | {{val|100|u=MB/s}}<ref>[https://books.google.com/books?id=XBvHNQzM2P0C&dq=APbus+MIPS+mhz&pg=PA7 Local Area Networks Newsletter by Paul Polishuk, September 1992, Page 7] (APbus used in Sony NeWS and NEC UP4800 workstations and NEC EWS4800 servers after VMEbus and before switch to PCI)</ref> ||
|-
| [[Sbus]] 32-bit/25&nbsp;MHz || align=right | '''{{val|800|u=Mbit/s}}''' || align=right | {{val|100|u=MB/s}} || 1989
|-
| DEC TURBOchannel 32-bit/25&nbsp;MHz || align=right | '''{{val|800|u=Mbit/s}}''' || align=right | {{val|100|u=MB/s}} ||
|-
| [[Local Bus 98]] 32-bit/33&nbsp;MHz || align=right | '''{{val|1056|u=Mbit/s}}''' || align=right | {{val|132|u=MB/s}}<ref>[[:ja:98ローカルバス|Japan wikipedia article]], Bus used in NEC PC-9821 series</ref> ||
|-
| [[VESA Local Bus]] (VLB) 32-bit/33&nbsp;MHz || align=right | '''{{val|1067|u=Mbit/s}}''' || align=right | {{val|133.33|u=MB/s}} || 1992
|-
| [[Peripheral Component Interconnect|PCI]] 32-bit/33&nbsp;MHz || align=right | '''{{val|1067|u=Mbit/s}}''' || align=right | {{val|133.33|u=MB/s}} || 1993
|-
| [[GSC bus|HP GSC-1X]] || align=right | '''{{val|1136|u=Mbit/s}}''' || align=right | {{val|142|u=MB/s}} ||
|-
| [[Zorro III]] 32-bit/[[asynchronous communication|async]] (eq. 37.5&nbsp;MHz)<ref>[[Dave Haynie]], designer of the Zorro III bus, claims in [https://groups.google.com/g/comp.sys.amiga/c/RcwFy7rKylQ/m/kvmjH0ynMsUJ?pli=1 this] posting that the theoretical max of the Zorro III bus can be derived by the timing information given in ''chapter 5'' of the [http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf Zorro III technical specification] {{Webarchive|url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf |date=2012-07-16}}.</ref><ref>Dave Haynie, designer of the Zorro III bus, states in [http://groups.google.com/group/comp.sys.amiga.advocacy/msg/42ecbcbae063cfe1?dmode=source this] posting that Zorro III is an [[asynchronous I/O|asynchronous]] bus and therefore does not have a classical MHz rating. A maximum theoretical MHz value may be derived by examining timing constraints detailed in the [http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf Zorro III technical specification] {{Webarchive|url=https://web.archive.org/web/20120716212151/http://www.thule.no/haynie/zorroiii/docs/zorro3.pdf |date=2012-07-16}}, which should yield about 37.5 MHz. No existing implementation performs to this level.</ref> || align=right | '''{{val|1200|u=Mbit/s}}''' || align=right | {{val|150|u=MB/s}}<ref>Dave Haynie, designer of the Zorro III bus, claims in [http://groups.google.com/group/comp.sys.amiga.hardware/msg/03b8cec336310e4a?dmode=source this] posting that Zorro III has a max burst rate of 150 MB/s.</ref> || 1990
|-
| VESA Local Bus (VLB) 32-bit/40&nbsp;MHz || align=right | '''{{val|1280|u=Mbit/s}}''' || align=right | {{val|160|u=MB/s}} || 1992
|-
| Sbus 64-bit/25&nbsp;MHz || align=right | '''{{val|1.6|u=Gbit/s}}''' || align=right | {{val|200|u=MB/s}} || 1995
|-
| [[GSC bus|HP GSC-2X]] || align=right | '''{{val|2.048|u=Gbit/s}}''' || align=right | {{val|256|u=MB/s}} ||
|-
| PCI 64-bit/33&nbsp;MHz || align=right | '''{{val|2.133|u=Gbit/s}}''' || align=right | {{val|266.7|u=MB/s}} || 1993
|-
| PCI 32-bit/66&nbsp;MHz || align=right | '''{{val|2.133|u=Gbit/s}}''' || align=right | {{val|266.7|u=MB/s}} || 1995
|-
| [[Accelerated Graphics Port|AGP]] 1× || align=right | '''{{val|2.133|u=Gbit/s}}''' || align=right | {{val|266.7|u=MB/s}} || 1997
|-
| [[PCI Express]] 1.0 (×1 link){{efn|name="pci-e"|Note that PCI Express 1.0/2.0 lanes use an [[8b/10b encoding]] scheme.}} || align=right | '''{{val|2.5|u=Gbit/s}}''' || align=right | {{val|250|u=MB/s}} {{ref label|8b-10b|z|z}} || 2004
|-
| [[RapidIO]] Gen1 1× || align=right | '''{{val|2.5|u=Gbit/s}}''' || align=right | {{val|312.5|u=MB/s}} ||
|-
| HIO bus || align=right | '''{{val|2.560|u=Gbit/s}}''' || align=right | {{val|320|u=MB/s}} ||
|-
| [[GIO]]64 64-bit/40&nbsp;MHz || align=right | '''{{val|2.560|u=Gbit/s}}''' || align=right | {{val|320|u=MB/s}} ||
|-
| PCI Express 2.0 (×1 link){{efn|name="pci-e2"}} || align=right | '''{{val|5|u=Gbit/s}}''' || align=right | {{val|500|u=MB/s}} {{ref label|8b-10b|z|z}} || 2007
|-
| AGP 2× || align=right | '''{{val|4.266|u=Gbit/s}}''' || align=right | {{val|533.3|u=MB/s}} || 1997
|-
| PCI 64-bit/66&nbsp;MHz || align=right | '''{{val|4.266|u=Gbit/s}}''' || align=right | {{val|533.3|u=MB/s}} ||
|-
| [[PCI-X]] DDR 16-bit || align=right | '''{{val|4.266|u=Gbit/s}}''' || align=right | {{val|533.3|u=MB/s}} ||
|-
| [[RapidIO]] Gen2 1× || align=right | '''{{val|5|u=Gbit/s}}''' || align=right | {{val|625|u=MB/s}} ||
|-
| PCI 64-bit/100&nbsp;MHz || align=right | '''{{val|6.4|u=Gbit/s}}''' || align=right | {{val|800|u=MB/s}} ||
|-
| PCI Express 3.0 (×1 link){{efn|name="pci-e3"|PCIe 3.0 increases the bandwidth from 5&nbsp;GT/s to 8&nbsp;GT/s and switches to 128b-130b encoding}} || align=right | '''{{val|8|u=Gbit/s}}''' || align=right | {{val|984.6|u=MB/s}} {{ref label|128b-130b|y|y}} || 2011
|-
| [[Unified Media Interface]] (UMI) (×4 link) || align=right | '''{{val|10|u=Gbit/s}}''' || align=right | {{val|1|u=GB/s}} {{ref label|8b-10b|z|z}} || 2011
|-
| [[Direct Media Interface]] (DMI) (×4 link) || align=right | '''{{val|10|u=Gbit/s}}''' || align=right | {{val|1|u=GB/s}} {{ref label|8b-10b|z|z}} || 2004
|-
| [[Enterprise Southbridge Interface]] (ESI) || align=right | '''{{val|8|u=Gbit/s}}''' || align=right | {{val|1|u=GB/s}} ||
|-
| PCI Express 1.0 (×4 link){{efn|name="pci-e"}} || align=right | '''{{val|10|u=Gbit/s}}''' || align=right | {{val|1|u=GB/s}} {{ref label|8b-10b|z|z}} || 2004
|-
| AGP 4× || align=right | '''{{val|8.533|u=Gbit/s}}''' || align=right | {{val|1.067|u=GB/s}} || 1998
|-
| [[PCI-X]] 133 || align=right | '''{{val|8.533|u=Gbit/s}}''' || align=right | {{val|1.067|u=GB/s}} ||
|-
| PCI-X QDR 16-bit || align=right | '''{{val|8.533|u=Gbit/s}}''' || align=right | {{val|1.067|u=GB/s}} ||
|-
| [[InfiniBand]] single 4×<ref name="infiniband">InfiniBand SDR, DDR and QDR use an [[8b/10b encoding]] scheme.</ref> || align=right | '''{{val|8|u=Gbit/s}}''' || align=right | {{val|1|u=GB/s}} {{ref label|8b-10b|z|z}} ||
|-
| [[RapidIO]] Gen1 4× || align=right | '''{{val|10|u=Gbit/s}}''' || align=right | {{val|1.25|u=GB/s}} ||
|-
| [[RapidIO]] Gen2 2× || align=right | '''{{val|10|u=Gbit/s}}''' || align=right | {{val|1.25|u=GB/s}} ||
|-
| [[Ultra Port Architecture|UPA]] || align=right | '''{{val|15.360|u=Gbit/s}}''' || align=right | {{val|1.92|u=GB/s}} ||
|-
| Unified Media Interface 2.0 (UMI 2.0; ×4 link) || align=right | '''{{val|20|u=Gbit/s}}''' || align=right | {{val|2|u=GB/s}} {{ref label|8b-10b|z|z}} || 2012
|-
| [[Direct Media Interface]] 2.0 (DMI 2.0; ×4 link) || align=right | '''{{val|20|u=Gbit/s}}''' || align=right | {{val|2|u=GB/s}} {{ref label|8b-10b|z|z}} || 2011
|-
| PCI Express 1.0 (×8 link){{efn|name="pci-e"}} || align=right | '''{{val|20|u=Gbit/s}}''' || align=right | {{val|2|u=GB/s}} {{ref label|8b-10b|z|z}} || 2004
|-
| PCI Express 2.0 (×4 link){{efn|name="pci-e2"}} || align=right | '''{{val|20|u=Gbit/s}}''' || align=right | {{val|2|u=GB/s}} {{ref label|8b-10b|z|z}} || 2007
|-
| AGP 8× || align=right | '''{{val|17.066|u=Gbit/s}}''' || align=right | {{val|2.133|u=GB/s}} || 2002
|-
| PCI-X DDR || align=right | '''{{val|17.066|u=Gbit/s}}''' || align=right | {{val|2.133|u=GB/s}} ||
|-
| [[RapidIO]] Gen2 4× || align=right | '''{{val|20|u=Gbit/s}}''' || align=right | {{val|2.5|u=GB/s}} ||
|-
| [[Sun JBus]] (200&nbsp;MHz) || align=right | '''{{val|20.48|u=Gbit/s}}''' || align=right | {{val|2.56|u=GB/s}} || 2003
|-
| [[HyperTransport]] (800&nbsp;MHz, 16-pair) || align=right | '''{{val|25.6|u=Gbit/s}}''' || align=right | {{val|3.2|u=GB/s}} || 2001
|-
| PCI Express 3.0 (×4 link){{efn|name="pci-e3"}} || align=right | '''{{val|32|u=Gbit/s}}''' || align=right | {{val|3.94|u=GB/s}} {{ref label|128b-130b|y|y}} || 2011
|-
| HyperTransport (1&nbsp;GHz, 16-pair) || align=right | '''{{val|32|u=Gbit/s}}''' || align=right | {{val|4|u=GB/s}} ||
|-
| PCI Express 1.0 (×16 link){{efn|name="pci-e"}} || align=right | '''{{val|40|u=Gbit/s}}''' || align=right | {{val|4|u=GB/s}} {{ref label|8b-10b|z|z}} || 2004
|-
| PCI Express 2.0 (×8 link){{efn|name="pci-e2"|PCIe 2.0 effectively doubles the bus standard's bandwidth from 2.5&nbsp;GT/s to 5&nbsp;GT/s}} || align=right | '''{{val|40|u=Gbit/s}}''' || align=right | {{val|4|u=GB/s}} {{ref label|8b-10b|z|z}} || 2007
|-
| PCI-X QDR || align=right | '''{{val|34.133|u=Gbit/s}}''' || align=right | {{val|4.266|u=GB/s}} ||
|-
| AGP 8× 64-bit || align=right | '''{{val|34.133|u=Gbit/s}}''' || align=right | {{val|4.266|u=GB/s}} ||
|-
| [[RapidIO]] Gen2 8x || align=right | '''{{val|40|u=Gbit/s}}''' || align=right | {{val|5|u=GB/s}} ||
|-
| [[Direct Media Interface]] 3.0 (DMI 3.0; ×4 link) || align=right | '''{{val|31.5|u=Gbit/s}}''' || align=right | {{val|3.94|u=GB/s}} {{ref label|128b-130b|y|y}} || 2015
|-
| [[Compute Express Link|CXL Specification 3.0]] & 3.1 (×1 link) || align="right" |'''{{val|60.504|u=Gbit/s}}''' || align=right | {{val|7.563|u=GB/s}}|| 2022, 2023
|-
| PCI Express 3.0 (×8 link){{efn|name="pci-e3"}} || align=right | '''{{val|64|u=Gbit/s}}''' || align=right | {{val|7.88|u=GB/s}} {{ref label|128b-130b|y|y}} || 2011
|-
| PCI Express 2.0 (×16 link){{efn|name="pci-e3"}} || align=right | '''{{val|80|u=Gbit/s}}''' || align=right | {{val|8|u=GB/s}} {{ref label|8b-10b|z|z}} || 2007
|-
| [[RapidIO]] Gen2 16x || align=right | '''{{val|80|u=Gbit/s}}''' || align=right | {{val|10|u=GB/s}} ||
|-
| PCI Express 5.0 (×4 link) || align="right" |'''{{val|128|u=Gbit/s}}''' || align=right | {{val|15.75|u=GB/s}}{{ref label|128b-130b|y|y}}|| 2019
|-
| PCI Express 3.0 (×16 link){{efn|name="pci-e3"}} || align=right | '''{{val|128|u=Gbit/s}}''' || align=right | {{val|15.75|u=GB/s}} {{ref label|128b-130b|y|y}} || 2011
|-
|[[Coherent Accelerator Processor Interface|CAPI]]|| align="right" | '''{{val|128|u=Gbit/s}}''' || align="right" |{{val|15.75|u=GB/s}} {{ref label|128b-130b|y|y}} || 2014
|-
| [[QPI]] (4.80GT/s, 2.40&nbsp;GHz) || align=right | '''{{val|153.6|u=Gbit/s}}''' || align=right | {{val|19.2|u=GB/s}} ||
|-
| HyperTransport 2.0 (1.4&nbsp;GHz, 32-pair) || align=right | '''{{val|179.2|u=Gbit/s}}''' || align=right | {{val|22.4|u=GB/s}} || 2004
|-
| [[QPI]] (5.86GT/s, 2.93&nbsp;GHz) || align=right | '''{{val|187.52|u=Gbit/s}}''' || align=right | {{val|23.44|u=GB/s}} ||
|-
| [[QPI]] (6.40GT/s, 3.20&nbsp;GHz) || align=right | '''{{val|204.8|u=Gbit/s}}''' || align=right | {{val|25.6|u=GB/s}} ||
|-
| [[QPI]] (7.2GT/s, 3.6&nbsp;GHz) || align=right | '''{{val|230.4|u=Gbit/s}}''' || align=right | {{val|28.8|u=GB/s}} || 2012
|-
| PCI Express 6.0 (×4 link) || align="right" |'''{{val|242|u=Gbit/s}}''' || align=right | {{val|30.25|u=GB/s}}{{ref label|242B-256B|w|w}}|| 2022
|-
| PCI Express 4.0 (×16 link)<ref>{{cite news |last1=Born |first1=Eric |title=PCIe 4.0 specification finally out with 16 GT/s on tap |url=https://techreport.com/news/32064/pcie-4-0-specification-finally-out-with-16-gts-on-tap/ |access-date=21 February 2018 |publisher=Tech Report |date=8 June 2017}}</ref> || align=right | '''{{val|256|u=Gbit/s}}''' || align=right | {{val|31.51|u=GB/s}}{{ref label|128b-130b|y|y}}|| 2018
|-
| [[Coherent Accelerator Processor Interface|CAPI 2]] || align=right | '''{{val|256|u=Gbit/s}}''' || align=right | {{val|31.51|u=GB/s}}{{ref label|128b-130b|y|y}} || 2016
|-
| [[QPI]] (8.0GT/s, 4.0&nbsp;GHz) || align=right | '''{{val|256.0|u=Gbit/s}}''' || align=right | {{val|32.0|u=GB/s}} || 2012
|-
| [[QPI]] (9.6GT/s, 4.8&nbsp;GHz) || align=right | '''{{val|307.2|u=Gbit/s}}''' || align=right | {{val|38.4|u=GB/s}} || 2014
|-
| HyperTransport 3.0 (2.6&nbsp;GHz, 32-pair) || align=right | '''{{val|332.8|u=Gbit/s}}''' || align=right | {{val|41.6|u=GB/s}} || 2006
|-
| HyperTransport 3.1 (3.2&nbsp;GHz, 32-pair) || align=right | '''{{val|409.6|u=Gbit/s}}''' || align=right | {{val|51.2|u=GB/s}} || 2008
|-
| [[Compute Express Link|CXL Specification 1.x]] & 2.0 (×16 link) || align="right" |'''{{val|512|u=Gbit/s}}''' || align=right | {{val|63.02|u=GB/s}}|| 2019, 2020
|-
| PCI Express 5.0 (×16 link) <ref>{{cite web |url=https://www.anandtech.com/show/14447/pcisig-finalizes-pcie-50-specification |title=PCI-SIG Finalizes PCIe 5.0 Specification: x16 Slots to Reach 64GB/sec |last=Smith |first=Ryan |website=www.anandtech.com |access-date=2019-06-26}}</ref>|| align="right" |'''{{val|512|u=Gbit/s}}''' || align=right | {{val|63.02|u=GB/s}}{{ref label|128b-130b|y|y}}|| 2019
|-
| [[NVLink]] 1.0 || align=right | '''{{val|640|u=Gbit/s}}''' || align=right | {{val|80|u=GB/s}} || 2016
|-
| PCI Express 6.0 (×16 link) <ref>{{Cite web|url=https://www.anandtech.com/show/17203/pcie-60-specification-finalized-x16-slots-to-reach-128gbps|title = PCI Express 6.0 Specification Finalized: X16 Slots to Reach 128GBps}}</ref> || align="right" |'''{{val|968|u=Gbit/s}}''' || align=right | {{val|121|u=GB/s}}{{ref label|242B-256B|w|w}}|| 2022
|-
| [[Compute Express Link|CXL Specification 3.0]] & 3.1 (×16 link) || align="right" |'''{{val|968|u=Gbit/s}}''' || align=right | {{val|121|u=GB/s}}|| 2022, 2023
|-
| NVLink 2.0 || align=right | '''{{val|1.2|u=Tbit/s}}''' || align=right | {{val|150|u=GB/s}} ||2017
|-
| PCI Express 7.0 (×16 link) || align="right" |'''{{val|1.936|u=Tbit/s}}''' || align=right | {{val|242|u=GB/s}}{{ref label|242B-256B|w|w}}|| 2025
|-
| [[Infinity Fabric]] (Max. theoretical) || align=right | '''{{val|4.096|u=Tbit/s}}''' || align=right | {{val|512|u=GB/s}} ||2017
|}

{{note label|lpc|x|x}} LPC protocol includes high overhead. While the gross data rate equals 33.3 million 4-bit-transfers per second (or {{val|16.67|u=MB/s}}), the fastest transfer, firmware read, results in {{val|15.63|u=MB/s}}. The next fastest bus cycle, 32-bit ISA-style DMA write, yields only {{val|6.67|u=MB/s}}. Other transfers may be as low as {{val|2|u=MB/s}}.<ref name="lpc-spec">[https://www.intel.com/content/www/us/en/design/technologies-and-topics/low-pin-count-interface-specification.html Intel LPC Interface Specification 1.1]</ref>

{{note label|128b-130b|y|y}} Uses [[128b/130b]] encoding, meaning that about 1.54% of each transfer is used for error detection instead of carrying data between the hardware components at each end of the interface. For example, a single link PCIe 3.0 interface has an {{nowrap|8 Gbit/s}} transfer rate, yet its usable bandwidth is only about {{nowrap|7.88 Gbit/s}}.

{{note label|8b-10b|z|z}} Uses [[8b/10b encoding]], meaning that 20% of each transfer is used by the interface instead of carrying data from between the hardware components at each end of the interface. For example, a single link PCIe 1.0 has a {{nowrap|2.5 Gbit/s}} transfer rate, yet its usable bandwidth is only {{nowrap|2 Gbit/s}} (250&nbsp;{{not a typo|MB/s}}).

{{note label|242B-256B|w|w}} Uses [[PAM-4]] encoding and a 256 bytes [[flit (computer networking)|FLIT]] block, of which 14 bytes are [[forward error correction|FEC]] and [[cyclic redundancy check|CRC]], meaning that 5.47% of total data rate is used for error detection and correction instead of carrying data. For example, a single link PCIe 6.0 interface has a {{nowrap|64 Gbit/s}} total transfer rate, yet its usable bandwidth is only {{nowrap|60.5 Gbit/s}}.