Editing SPARC (section)

==Open source implementations==
Several fully [[open-source hardware|open source]] implementations of the SPARC architecture exist:

* [[LEON]], a 32-bit [[radiation hardening|radiation-tolerant]], SPARC V8 implementation, designed especially for space use. [[Source code]] is written in [[VHSIC Hardware Description Language|VHDL]], and licensed under the [[GNU General Public License|GPL]].
* [[OpenSPARC]] [[UltraSPARC T1|T1]], released in 2006, a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9 (Level 1). Source code is written in [[Verilog]], and licensed under many licenses.  Most OpenSPARC T1 source code is licensed under the GPL.  Source based on existent open source projects will continue to be licensed under their current licenses.  Binary programs are licensed under a binary [[software license agreement]].
* [[S1 Core|S1]], a 64-bit Wishbone compliant CPU core based on the OpenSPARC T1 design. It is a single UltraSPARC V9 core capable of 4-way SMT. Like the T1, the source code is licensed under the GPL.
* [[OpenSPARC]] [[UltraSPARC T2|T2]], released in 2008, a 64-bit, 64-thread implementation conforming to the UltraSPARC Architecture 2007 and to SPARC Version 9 (Level 1). Source code is written in Verilog, and licensed under many licenses.  Most OpenSPARC T2 source code is licensed under the GPL. Source based on existing open source projects will continue to be licensed under their current licenses.  Binary programs are licensed under a binary Software License Agreement.

A fully [[open-source software|open source]] simulator for the SPARC architecture also exists:

* [https://web.archive.org/web/20160529045508/https://sites.google.com/site/rampgold/ RAMP Gold], a 32-bit, 64-thread SPARC Version 8 implementation, designed for FPGA-based architecture simulation. RAMP Gold is written in ~36,000 lines of [[SystemVerilog]], and licensed under the [[BSD licenses]].