Editing System Management Bus (section)

== Replacement ==
[[DDR5]] introduces [[I3C (bus)|I3C]] for its presence detect communication, replacing SMBus.<ref>{{cite web |title=MIPI I3C Basic in JEDEC DDR5: A Sum Greater Than Its Parts |url=https://www.mipi.org/blog/mipi-i3c-basic-in-jedec-ddr5-a-sum-greater-than-its-parts |website=www.mipi.org |language=en-us}}</ref>

[[PCI express]] devices commonly use SMBus as a "out-of-band management port". However, device vendors frequently use SMBus multiplexers (Mux) to manage address clashes (which are in turn caused by them ''not'' implementing the Address Resolution Protocol), causing link interruptions that break [[Management Component Transport Protocol]] and other protocols when the Mux switches targets. To solve this problem, SNIA's [[Enterprise and Data Center Standard Form Factor]] version 3.1 (January 2023) describes a way to use I3C basic over the PCIe two-wire interface.<ref name=pci-2023>{{cite web |last1=Jurski |first1=Janusz |last2=Loewen |first2=Myron |last3=Constantine |first3=Anthony |last4=Orozco |first4=Juan |last5=Kelly |first5=Bryan |last6=Lukwinski |first6=Zbigniew |title=Overcoming SMBus Limitations with I3C |url=https://storagedeveloper.org/sites/default/files/SDC/2023/presentations/SNIA-SDC23-Jurski-Loewen-Constantine-Orozco-Overcoming-SMBus-limitations-with-I3C.pdf}} [https://www.snia.org/educational-library/overcoming-smbus-limitations-i3c-2023 video]</ref> [[NVM Express]] 2.1 (August 2024) is also reworded to allow the use of I3C, "to match the new conventions used by SNIA SFF TA's EDSFF and PCI-SIG specifications for I3C".<ref>{{cite web |title=Changes in NVM Express Revision 2.1 - NVM Express |url=https://nvmexpress.org/specification/changes-in-nvm-express-revision-2-1/ |date=23 August 2024}}</ref>