Editing Verilog (section)

==Operators==
Note: These operators are ''not'' shown in order of precedence.
{| class=wikitable
|-
! Operator type || Operator symbols || Operation performed
|-
| rowspan=5|Bitwise || ~ || Bitwise NOT (1's complement)
|-
|                      & || Bitwise AND
|-
|              <nowiki>|</nowiki> || Bitwise OR
|-
|                      ^ || Bitwise XOR
|-
|                      ~^ or ^~ || Bitwise XNOR
|-
| rowspan=3|Logical           || ! || NOT
|-
| && || AND
|-
| <nowiki>||</nowiki> ||  OR
|-
| rowspan=6|Reduction || & || Reduction AND
|-
| ~& || Reduction NAND
|-
| <nowiki>|</nowiki> || Reduction OR
|-
| <nowiki>~|</nowiki> || Reduction NOR
|-
| ^ || Reduction XOR
|-
| ~^ or ^~ || Reduction XNOR
|-
| rowspan=6|Arithmetic || + || Addition
|-
| - || Subtraction
|-
| - || 2's complement
|-
| * || Multiplication
|-
| / || Division
|-
| ** || Exponentiation (*Verilog-2001)
|-
| rowspan=8| Relational || > || Greater than
|-
| < || Less than
|-
| >= || Greater than or equal to
|-
| <= || Less than or equal to
|-
| == || Logical equality (bit-value 1'bX is removed from comparison)
|-
| != || Logical inequality (bit-value 1'bX is removed from comparison)
|-
| === || 4-state logical equality (bit-value 1'bX is taken as literal)
|-
| !== || 4-state logical inequality (bit-value 1'bX is taken as literal)
|-
| rowspan=4| Shift || >> || [[Logical shift|Logical right shift]]
|-
| << || [[Logical shift|Logical left shift]]
|-
| >>> || [[Arithmetic shift|Arithmetic right shift]] (*Verilog-2001)
|-
| <<< || [[Arithmetic shift|Arithmetic left shift]] (*Verilog-2001)
|-
| Concatenation || <nowiki>{, }</nowiki> || Concatenation
|-
| Replication || <nowiki>{n{m}}</nowiki> || Replicate value m for n times
|-
| Conditional || ? : || Conditional
|}