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DEC Alpha
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==Extensions== ===Byte-Word Extensions (BWX)=== Later Alphas include byte-word extensions, a set of instructions to manipulate 8-bit and 16-bit data types. These instructions were first introduced in the [[Alpha 21164#Alpha 21164 (EV56)|21164A]] (EV56) microprocessor and are present in all subsequent implementations. These instructions perform operations that formerly required multiple instructions to implement, which improves code density and the performance of certain applications. BWX also makes the emulation of x86 machine code and the writing of [[device driver]]s easier.<ref>{{Cite journal |doi=10.1109/JSSC.1996.542313 |bibcode=1996IJSSC..31.1687G |title=A 433-MHz 64-b quad-issue RISC microprocessor |journal=IEEE Journal of Solid-State Circuits |volume=31 |issue=11 |pages=1687β1696 |year=1996 |last1=Gronowski |first1=P. E. |last2=Bowhill |first2=W. J. |last3=Donchin |first3=D. R. |last4=Blake-Campos |first4=R. P. |last5=Carlson |first5=D. A. |last6=Equi |first6=E. R. |last7=Loughlin |first7=B. J. |last8=Mehta |first8=S. |last9=Mueller |first9=R. O. |last10=Olesin |first10=A. |last11=Noorlag |first11=D. J. W. |last12=Preston |first12=R. P. |s2cid=39280205}}</ref> {| class="wikitable" |- ! width="120" | Mnemonic ! width="360" | Instruction |- | <code>LDBU</code> | Load Zero-Extended Byte from Memory to Register |- | <code>LDWU</code> | Load Zero-Extended Word from Memory to Register |- | <code>SEXTB</code> | Sign Extend Byte |- | <code>SEXTW</code> | Sign Extend Word |- | <code>STB</code> | Store Byte from Register to Memory |- | <code>STW</code> | Store Word from Register to Memory |- |} ===Motion Video Instructions (MVI)=== Motion Video Instructions (MVI) was an instruction set extension to the Alpha ISA that added instructions for [[single instruction, multiple data]] (SIMD) operations.<ref>Gwennap, Linley (18 November 1996). "Digital, MIPS Add Multimedia Extensions". ''[[Microprocessor Report]]''.</ref> Alpha implementations that implement MVI, in chronological order, are the [[Alpha 21164#Alpha 21164PC|Alpha 21164PC]] (PCA56 and PCA57), [[Alpha 21264]] (EV6) and [[Alpha 21364]] (EV7). Unlike most other SIMD instruction sets of the same period, such as [[MIPS architecture|MIPS]]' [[MDMX]] or [[SPARC]]'s [[Visual Instruction Set]], but like [[PA-RISC]]'s [[Multimedia Acceleration eXtensions]] (MAX-1, MAX-2), MVI was a simple instruction set composed of a few instructions that operate on integer data types stored in existing integer registers. MVI's simplicity is due to two reasons. Firstly, Digital had determined that the [[Alpha 21164]] was already capable of performing [[DVD]] decoding through software, therefore not requiring hardware provisions for the purpose, but was inefficient in [[MPEG-2]] encoding. The second reason is the requirement to retain the fast cycle times of implementations. Adding many instructions would have complicated and enlarged the instruction decode logic, reducing an implementation's clock frequency. MVI consists of 13 instructions: {| class="wikitable" |- ! width="120" | Mnemonic ! width="360" | Instruction |- | <code>MAXSB8</code> | Vector Signed Byte Maximum |- | <code>MAXSW4</code> | Vector Signed Word Maximum |- | <code>MAXUB8</code> | Vector Unsigned Byte Maximum |- | <code>MAXUW4</code> | Vector Unsigned Word Maximum |- | <code>MINSB8</code> | Vector Signed Byte Minimum |- | <code>MINSW4</code> | Vector Signed Word Minimum |- | <code>MINUB8</code> | Vector Unsigned Byte Minimum |- | <code>MINUW4</code> | Vector Unsigned Word Minimum |- | <code>PERR</code> | Pixel Error |- | <code>PKLB</code> | Pack Longwords to Bytes |- | <code>PKWB</code> | Pack Words to Bytes |- | <code>UNPKBL</code> | Unpack Bytes to Longwords |- | <code>UNPKBW</code> | Unpack Bytes to Words |- |} {{Multimedia extensions}} ===Floating-point Extensions (FIX)=== Floating-point extensions (FIX) are an extension to the Alpha Architecture. It introduces nine instructions for floating-point square-root and for transferring data to and from the integer registers and floating-point registers. The [[Alpha 21264]] (EV6) is the first microprocessor to implement these instructions. {| class="wikitable" |- ! width="120" | Mnemonic ! width="360" | Instruction |- | <code>FTOIS</code> | Floating-point to Integer Register Move, S_floating |- | <code>FTOIT</code> | Floating-point to Integer Register Move, T_floating |- | <code>ITOFF</code> | Integer to Floating-point Register Move, F_floating |- | <code>ITOFS</code> | Integer to Floating-point Register Move, S_floating |- | <code>ITOFT</code> | Integer to Floating-point Register Move, T_floating |- | <code>SQRTF</code> | Square root F_floating |- | <code>SQRTG</code> | Square root G_floating |- | <code>SQRTS</code> | Square root S_floating |- | <code>SQRTT</code> | Square root T_floating |- |} ===Count Extensions (CIX)=== Count Extensions (CIX) is an extension to the architecture which introduces three instructions for counting bits. These instructions are categorized as integer arithmetic instructions. They were first implemented on the [[Alpha 21264#Alpha 21264A|Alpha 21264A]] (EV67). {| class="wikitable" |- ! width="120" | Mnemonic ! width="360" | Instruction |- | <code>CTLZ</code> | Count Leading Zero |- | <code>CTPOP</code> | Count Population |- | <code>CTTZ</code> | Count Trailing Zero |- |}
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