Open main menu
Home
Random
Recent changes
Special pages
Community portal
Preferences
About Wikipedia
Disclaimers
Incubator escapee wiki
Search
User menu
Talk
Dark mode
Contributions
Create account
Log in
Editing
Data General Nova
(section)
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
===Memory and I/O=== The smallest unit of addressable and writable memory is the 16-bit word; byte addressing is not supported. The first models were available with 8 [[kilo-|K]] [[word (computer architecture)|words]] of [[magnetic-core memory]] as an option, one that practically everyone had to buy, bringing the system cost up to $7,995. This core memory board was organized in planar fashion as four groups of four banks, each bank carrying two sets of core in a 64 by 64 matrix; thus there were 64 x 64 = 4096 bits per set, x 2 sets giving 8,192 bits, x 4 banks giving 32,768 bits, x 4 groups giving a total of 131,072 bits, and this divided by the machine word size of 16 bits gave 8,192 words of memory. The core on this 8K word memory board occupied a centrally located "board-on-a-board", 5.25" wide by 6.125" high, and was covered by a protective plate. It was surrounded by the necessary support driver read-write-rewrite circuitry. All of the core and the corresponding support electronics fit onto a single standard 15 x {{convert|15|in|mm|adj=on}} board. Up to 32K of such core [[random-access memory|RAM]] could be supported in one external expansion box. [[Semiconductor]] [[read-only memory|ROM]] was already available at the time, and RAM-less systems (i.e. with ROM only) became popular in many industrial settings. The original Nova machines ran at approximately 200 [[kilohertz|kHz]], but its SuperNova was designed to run at up to 3 MHz when used with special semiconductor main memory. The standardized [[backplane]] and [[input/output|I/O]] signals created a simple, efficient I/O design that made interfacing programmed I/O and Data Channel devices to the Nova simple compared to competing machines. In addition to its dedicated I/O bus structure, the Nova backplane had [[wire wrap]] pins that could be used for non-standard connectors or other special purposes.
Edit summary
(Briefly describe your changes)
By publishing changes, you agree to the
Terms of Use
, and you irrevocably agree to release your contribution under the
CC BY-SA 4.0 License
and the
GFDL
. You agree that a hyperlink or URL is sufficient attribution under the Creative Commons license.
Cancel
Editing help
(opens in new window)