Editing Flash memory (section)

===Vertical NAND===
[[File:NAND_Flash_Bit_Cost_from_2D_to_3D.png|thumb|right|300px|3D NAND continues scaling beyond 2D.]]
Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a [[charge trap flash]] architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells.<ref name="vnand">{{cite web |url=http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655 |title=Samsung moves into mass production of 3D flash memory |publisher=Gizmag.com |access-date=2013-08-27 |url-status=live |archive-url=https://web.archive.org/web/20130827091835/http://www.gizmag.com/samsung-v-nand-flash-chip-ssd/28655/ |archive-date=27 August 2013|date=27 August 2013 }}</ref> It is also sold under the trademark ''BiCS Flash'', which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND was first announced by [[Toshiba]] in 2007.<ref name="toshiba-3d">{{Cite news |last=Melanson |first=Donald |date=12 June 2007 |title=Toshiba announces new "3D" NAND flash technology |work=[[Engadget]] |url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/ |url-status=live |access-date=10 July 2019 |archive-url=https://web.archive.org/web/20221217224115/https://www.engadget.com/2007-06-12-toshiba-announces-new-3d-nand-flash-technology.html |archive-date=17 December 2022 }}</ref> V-NAND was first commercially manufactured by [[Samsung Electronics]] in 2013.<ref name="samsung-3d">{{Cite press release |date=13 August 2013 |title=Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |url-status=dead |archive-url=https://web.archive.org/web/20190414192036/https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/ |archive-date=14 April 2019 |publisher=[[Samsung]] }}</ref><ref name="samsung-3d-ee">{{Cite news |last=Clarke |first=Peter |date=8 August 2013 |title=Samsung Confirms 24 Layers in 3D NAND |work=[[EE Times]] |url=https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |url-status=live |archive-url=https://web.archive.org/web/20200219151255/https://www.eetimes.com/samsung-confirms-24-layers-in-3d-nand/ |archive-date=19 February 2020 }}</ref><ref name="samsung-20141009">{{Cite press release |date=9 October 2014 |title=Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory |url=https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |url-status=live |archive-url=https://web.archive.org/web/20230330135736/https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory |archive-date=30 March 2023 |publisher=[[Samsung]] }}</ref><ref name="samsung-vnand-2014">{{Cite web |date=September 2014 |title=Samsung V-NAND technology |url=http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |url-status=dead |archive-url=https://web.archive.org/web/20160327194431/http://www.samsung.com/us/business/oem-solutions/pdfs/V-NAND_technology_WP.pdf |archive-date=27 March 2016 |access-date=27 March 2016 |publisher=[[Samsung]] }}</ref>

====Structure====
V-NAND uses a [[charge trap flash]] geometry (which was commercially introduced in 2002 by [[AMD]] and [[Fujitsu]])<ref name="auto3"/> that stores charge on an embedded [[silicon nitride]] film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps a planar charge trap cell into a cylindrical form.<ref name="vnand" /> As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share the same silicon nitride material.<ref name="anandtech-20201109">{{Cite news |last=Tallis |first=Billy |date=9 November 2020 |title=Micron Announces 176-layer 3D NAND |work=[[AnandTech]] |url=https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |url-status=live |archive-url=https://web.archive.org/web/20231102133017/https://www.anandtech.com/show/16230/micron-announces-176layer-3d-nand |archive-date=2 November 2023 }}</ref> <!--the exact details of the V-NAND structure vary by manufacturer.-->

An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as the tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel.<ref name="vnand" />

Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to the serial-linked groups in which conventional NAND&nbsp;flash memory is configured.<ref name="vnand" /> There is also string stacking, which builds several 3D NAND memory arrays or "plugs"<ref>{{Cite web|url=https://blocksandfiles.com/2023/08/18/samsung-has-300-layer-nand-coming-with-430-layers-after-that/|title=Samsung has 300-layer NAND coming, with 430 layers after that – report|first=Chris|last=Mellor|date=18 August 2023}}</ref> separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm.<ref name="auto8"/><ref>{{Cite book|chapter-url=https://ieeexplore.ieee.org/document/9282426|title=2020 China Semiconductor Technology International Conference (CSTIC)|doi=10.1109/CSTIC49141.2020.9282426 |chapter=Manufacturing Challenges and Cost Evaluation of New Generation 3D Memories |date=2020 |last1=Dube |first1=Belinda Langelihle |pages=1–3 |isbn=978-1-7281-6558-5 |s2cid=229376195 }}</ref><ref name="auto9">{{Cite web |last=Choe |first=Jeongdong |date=2019 |title=Comparison of Current 3D NAND Chip & Cell Architecture |url=https://files.futurememorystorage.com/proceedings/2019/08-07-Wednesday/20190807_FTEC-202-1_Choe.pdf |pages=21, 24}}</ref>

====Construction====
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers.<ref name="vnand" />

The next step is to form a cylindrical hole through these layers. In practice, a 128&nbsp;[[Gbit]] V-NAND chip with 24 layers of memory cells requires about 2.9 billion such holes. Next, the hole's inner surface receives multiple coatings, first silicon dioxide, then silicon nitride, then a second layer of silicon dioxide. Finally, the hole is filled with conducting (doped) polysilicon.<ref name="vnand" />

====Performance====
{{As of|2013|post=,}} V-NAND flash architecture allows read and write operations twice as fast as conventional NAND and can last up to 10 times as long, while consuming 50 percent less power. They offer comparable physical bit density using 10-nm lithography but may be able to increase bit density by up to two orders of magnitude, given V-NAND's use of up to several hundred layers.<ref name="vnand" /> As of 2020, V-NAND chips with 160 layers are under development by Samsung.<ref name="techspot-20200420">{{Cite news |last=Potoroaca |first=Adrian |date=20 April 2020 |title=Samsung said to be developing industry's first 160-layer NAND flash memory chip |work=TechSpot |url=https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |url-status=live |archive-url=https://web.archive.org/web/20231102130037/https://www.techspot.com/news/84905-samsung-developing-industry-first-160-layer-nand-flash.html |archive-date=2 November 2023 }}</ref> As the number of layers increases, the capacity and endurance of flash memory may be increased.

====Cost====
[[File:3D NAND minimum cost example.png|thumb|right|300px|'''Minimum bit cost of 3D NAND from non-vertical sidewall.''' The top opening widens with more layers, counteracting the increase in bit density.]]
The wafer cost of a 3D NAND is comparable with scaled down (32&nbsp;nm or less) planar NAND flash.<ref>{{cite web|url=https://www.linkedin.com/pulse/toshibas-cost-model-3d-nand-frederick-chen|title=Toshiba's Cost Model for 3D NAND|website=www.linkedin.com}}</ref> However, with planar NAND scaling stopping at 16&nbsp;nm, the cost per bit reduction can continue by 3D NAND starting with 16 layers. However, due to the non-vertical sidewall of the hole etched through the layers; even a slight deviation leads to a minimum bit cost, i.e., minimum equivalent design rule (or maximum density), for a given number of layers; this minimum bit cost layer number decreases for smaller hole diameter.<ref>{{cite web |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |url=https://www.linkedin.com/pulse/calculating-maximum-density-equivalent-2d-design-rule-frederick-chen |website=linkedin.com |access-date=1 June 2022}}; {{cite web |url=https://semiwiki.com/lithography/296121-calculating-the-maximum-density-and-equivalent-2d-design-rule-of-3d-nand-flash/ |title=Calculating the Maximum Density and Equivalent 2D Design Rule of 3D NAND Flash |website=semwiki.com |access-date=1 June 2022}}</ref>