Editing Linear algebra (section)

=== Scientific computation ===
Nearly all [[scientific computation]]s involve linear algebra. Consequently, linear algebra algorithms have been highly optimized. [[Basic Linear Algebra Subprograms|BLAS]] and [[LAPACK]] are the best known implementations. For improving efficiency, some of them configure the algorithms automatically, at run time, to adapt them to the specificities of the computer ([[cache (computing)|cache]] size, number of available [[multi-core processor|cores]],&nbsp;...).

Since the 1960s there have been processors with specialized instructions<ref>{{cite book
 | title     = IBM System/36O Model 40 - Sum of Products Instruction-RPQ W12561 - Special Systems Feature
 | id        = L22-6902
 | publisher = [[IBM]]
 }}
</ref> for optimizing the operations of linear algebra, optional array processors<ref>{{cite book
 | title     = IBM System/360 Custom Feature Description: 2938 Array Processor Model 1, - RPQ W24563; Model 2, RPQ 815188
 | id        = A24-3519
 | publisher = [[IBM]]
 }}
</ref> under the control of a conventional processor, supercomputers<ref>{{cite journal
 | journal     = [[IEEE Transactions on Computers]]
 | title       = The ILLIAC IV Computer
 | last1       = Barnes
 | first1      = George
 | last2       = Brown
 | first2      = Richard
 | last3       = Kato
 | first3      = Maso
 | last4       = Kuck
 | first4      = David
 | last5       = Slotnick
 | first5      = Daniel
 | last6       = Stokes
 | first6      = Richard
 | date        = August 1968
 | volume      = C.17
 | number      = 8
 | pages       = 746–757
 | issn        = 0018-9340 
 | s2cid       = 206617237
 | doi         = 10.1109/tc.1968.229158
 | url         = http://gordonbell.azurewebsites.net/cgb%20files/computer%20structures%20readings%20and%20examples%201971.pdf
 | access-date = October 31, 2024
 }}
</ref><ref name="Star100HW">{{cite book
 | title       = Star-100 - Hardware Reference Manual
 | id          = 60256000
 | date        = December 15, 1975
 | version     = Revision 9
 | publisher   = [[Control Data Corporation]]
 | url         = http://bitsavers.trailing-edge.com/pdf/cdc/cyber/cyber_200/60256000_STAR-100hw_Dec75.pdf
 | access-date = October 31, 2024
 }}
</ref><ref name="cray1hw">{{cite book
 | title       = Cray-1 - Computer System - Hardware Reference Manual
 | id          = 2240004
 | date        = November 4, 1977
 | version     = Rev. C
 | publisher   = [[Cray Research, Inc.]]
 | url         = http://bitsavers.trailing-edge.com/pdf/cray/CRAY-1/2240004C_CRAY-1_Hardware_Reference_Nov77.pdf
 | access-date = October 31, 2024
 }}
</ref> designed for array processing and conventional processors augmented<ref>{{cite book
 | title       = IBM Enterprise Systems Architecture/370 and System/370 Vector Operations 
 | id          = SA22-7125-3
 | date        = August 1988
 | edition     = Fourth 
 | publisher   = [[IBM]]
 | url         = http://bitsavers.org/pdf/ibm/370/vectorFacility/SA22-7125-3_Vector_Operations_Aug88.pdf
 | access-date = October 31, 2024
 }}
</ref> with vector registers.

Some contemporary [[Processor (computing)|processor]]s, typically [[graphics processing units]] (GPU), are designed with a matrix structure, for optimizing the operations of linear algebra.<ref>{{Cite web |title=GPU Performance Background User's Guide |url=https://docs.nvidia.com/deeplearning/performance/dl-performance-gpu-background/index.html |access-date=2024-10-29 |website=NVIDIA Docs |language=en}}</ref>