Editing MIPS architecture (section)

=== MIPS16 ===
MIPS16 is an Application-Specific Extension for MIPS I through to V designed by [[LSI Logic]] and [[MIPS Technologies]], announced on October 21, 1996, alongside its first implementation, the LSI Logic TinyRISC processor.<ref>{{cite press release |title=Silicon Graphics Introduces Compact MIPS RISC Microprocessor Code For High Performance at a Low Cost |date=October 21, 1996}}</ref> MIPS16 was subsequently licensed by [[NEC Electronics]], [[Philips Semiconductors]], and [[Toshiba]] (among others); and implemented as an extension to the MIPS I, II, an III architectures. MIPS16 decreases the size of application by up to 40% by using 16-bit instructions instead of 32-bit instructions and also improves power efficiency, the instruction cache hit rate, and is equivalent in performance to its base architecture.<ref>{{cite book|last1=Sweetman|first1=Dominic|title=See MIPS Run|date=2007|publisher=Morgan Kaufmann Publishers|location=San Francisco, California|isbn=978-0-12-088421-6|pages=425–427|edition=2nd}}</ref> It is supported by hardware and software development tools from MIPS Technologies and other providers. MIPS16e is an improved version of MIPS16 first supported by MIPS32 and MIPS64 Release 1. MIPS16e2 is an improved version of MIPS16 that is supported by MIPS32 and MIPS64 (up to Release 5). Release 6 replaced it with microMIPS.