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Stack machine
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=== Interpreters === Interpreters for virtual stack machines are easier to build than interpreters for register machines; the logic for handling memory address modes is in just one place rather than repeated in many instructions. Stack machines also tend to have fewer variations of an opcode; one generalized opcode will handle both frequent cases and obscure corner cases of memory references or function call setup. (But code density is often improved by adding short and long forms for the same operation.) Interpreters for virtual stack machines are often slower than interpreters for other styles of virtual machine.<ref name="Shi-Gregg-Beatty-Ertle_2"/> This slowdown is worst when running on host machines with deep execution pipelines, such as current x86 chips. In some interpreters, the interpreter must execute a N-way switch jump to decode the next opcode and branch to its steps for that particular opcode. Another method for selecting opcodes is [[threaded code]]. The host machine's prefetch mechanisms are unable to predict and fetch the target of that indexed or indirect jump. So the host machine's execution pipeline must restart each time the hosted interpreter decodes another virtual instruction. This happens more often for virtual stack machines than for other styles of virtual machine.<ref name="Davis-Beatty-Casey-Gregg-Waldron_2005"/> One example is the [[Java (programming language)|Java]] programming language. Its canonical [[virtual machine]] is specified as an 8-bit stack machine. However, the [[Dalvik (software)|Dalvik]] virtual machine for Java used on [[Android (operating system)|Android]] [[smartphones]] is a 16-bit virtual-register machine - a choice made for efficiency reasons. Arithmetic instructions directly fetch or store local variables via 4-bit (or larger) instruction fields.<ref name="Bornstein_2008"/> Similarly version 5.0 of Lua replaced its virtual stack machine with a faster virtual register machine.<ref name="Lua5"/><ref name="Lua5_VM"/> Since Java virtual machine became popular, microprocessors have employed advanced [[branch predictor]]s for indirect jumps.<ref name="inria"/> This advance avoids most of pipeline restarts from N-way jumps and eliminates much of the instruction count costs that affect stack interpreters.
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