Editing Synchronous dynamic random-access memory (section)

== Generations ==
{| class="wikitable floatright"
|+ SDRAM feature map
! scope="col" | Type
! scope="col" | Feature changes<!-- That impacts interfacing to the memory chip -->
|-
! scope="row" | SDRAM
| {{Unbulleted list
| {{Nowrap|V{{Sub|cc}} {{=}} 3.3&nbsp;V}}
| Signal: [[Transistor–transistor logic#Sub-types|LVTTL]]
}}
|-
! scope="row" | [[DDR SDRAM|DDR1]]
| {{Unbulleted list
| Access is ≥&nbsp;2 words
| [[Double data rate|Double clocked]]
| {{Nowrap|V{{Sub|cc}} {{=}} 2.5&nbsp;V}}
| {{Nowrap|2.5&nbsp;−&nbsp;7.5&nbsp;ns}} per cycle
| Signal: [[Stub Series Terminated Logic|SSTL_2]] (2.5&nbsp;V)<ref name="edn-dramconsumer">{{cite web|title=The outlook for DRAMs in consumer electronics|url=https://www.edn.com/the-outlook-for-drams-in-consumer-electronics/|last=Graham |first=Allan |publisher=AspenCore Media |website=EDN|date=2007-01-12 |access-date=2021-04-13}}</ref>
}}
|-
! scope="row" | [[DDR2 SDRAM|DDR2]]
| Access is ≥&nbsp;4 words<br/> "Burst terminate" removed<br/> 4 units used in parallel<br/> {{Nowrap|1.25&nbsp;−&nbsp;5ns}} per cycle<br/> Internal operations are<br>&nbsp;at 1/2 the clock rate.<br/> Signal: [[Stub Series Terminated Logic|SSTL_18]] (1.8&nbsp;V)<ref name="edn-dramconsumer"/>
|-
! scope="row" | [[DDR3 SDRAM|DDR3]]
| Access is ≥&nbsp;8 words<br/> Signal: [[Stub Series Terminated Logic|SSTL_15]] (1.5&nbsp;V)<ref name="edn-dramconsumer"/><br/> Much longer CAS latencies
|-
! scope="row" | [[DDR4 SDRAM|DDR4]]
| {{Nowrap|V{{Sub|cc}} ≤&nbsp;1.2&nbsp;V}} point-to-point<br>(single module per channel)
|}

=== SDR ===
[[Image:Micron 48LC32M8A2-AB.jpg|thumb|upright=1.25|The 64&nbsp;MB{{binpre}} of sound memory on the [[Sound Blaster X-Fi|Sound Blaster X-Fi Fatality Pro]] [[sound card]] is built from 2 [[Micron Technology|Micron]] 48LC32M8A2 SDRAM chips. They run at 133&nbsp;MHz (7.5&nbsp;ns clock period) and have 8-bit wide data buses.<!-- x8 3.3V TSOP-54 CL=3 PC133 --><ref>{{cite web|title=SDRAM Part Catalog|url=http://www.micron.com/products/dram/sdram/partlist}} 070928 micron.com</ref>]]

Originally simply known as ''SDRAM'', single data rate SDRAM can accept one command and transfer one word of data per clock cycle. Chips are made with a variety of data bus sizes (most commonly 4, 8 or 16 bits), but chips are generally assembled into 168-pin [[DIMM]]s that read or write 64 (non-ECC) or 72 ([[ECC memory|ECC]]) bits at a time.

Use of the data bus is intricate and thus requires a complex DRAM controller circuit. This is because data written to the DRAM must be presented in the same cycle as the write command, but reads produce output 2 or 3 cycles after the read command. The DRAM controller must ensure that the data bus is never required for a read and a write at the same time.

Typical SDR SDRAM clock rates are 66, 100, and 133&nbsp;MHz (periods of 15, 10, and 7.5&nbsp;ns), respectively denoted PC66, PC100, and PC133. Clock rates up to 200&nbsp;MHz were available. It operates at a voltage of 3.3&nbsp;V.

This type of SDRAM is slower than the DDR variants, because only one word of data is transmitted per clock cycle (single data rate). But this type is also faster than its predecessors [[extended data out DRAM]] (EDO-RAM) and [[fast page mode DRAM]] (FPM-RAM) which took typically two or three clocks to transfer one word of data.

==== PC66 ====
'''PC66''' refers to internal removable computer [[random-access memory|memory]] standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC66 is Synchronous DRAM operating at a clock frequency of 66.66&nbsp;MHz, on a 64-bit bus, at a voltage of 3.3&nbsp;V. PC66 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. The theoretical bandwidth is 533&nbsp;MB/s. (1&nbsp;MB/s = one million bytes per second)

This standard was used by [[Original Intel Pentium (P5 microarchitecture)|Intel Pentium]] and [[AMD K6]]-based PCs. It also features in the Beige [[Power Mac G3]], early [[iBook]]s and [[PowerBook G3]]s. It is also used in many early [[Intel Celeron]] systems with a 66&nbsp;MHz [[front-side bus|FSB]]. It was superseded by the PC100 and PC133 standards.

==== PC100 ====
{{For|the Japanese home computer|NEC PC-100}}
[[Image:SDRAM 128MB 133MHz.jpg|thumb|upright=1.25|DIMM: 168 pins and two notches]]
'''PC100''' is a standard for internal removable computer [[random-access memory]], defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC100 refers to Synchronous DRAM operating at a clock frequency of 100&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC100 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] [[Computer form factor|form factor]]s. PC100 is [[backward compatible]] with PC66 and was superseded by the PC133 standard.

A module built out of 100&nbsp;MHz SDRAM chips is not necessarily capable of operating at 100&nbsp;MHz. The PC100 standard specifies the capabilities of the [[memory module]] as a whole. PC100 is used in many older computers; PCs around the late 1990s were the most common computers with PC100 memory.

==== PC133 ====
'''PC133''' is a computer memory standard defined by the [[Joint Electron Device Engineering Council|JEDEC]]. PC133 refers to [[SDR SDRAM]] operating at a clock frequency of 133&nbsp;MHz, on a 64-bit-wide bus, at a voltage of 3.3&nbsp;V. PC133 is available in 168-pin [[DIMM]] and 144-pin [[SO-DIMM]] form factors. PC133 is the fastest and final SDR SDRAM standard ever approved by the JEDEC, and delivers a bandwidth of 1.066&nbsp;GB per second ([133.33&nbsp;MHz * 64/8]=1.066&nbsp;GB/s). (1&nbsp;GB/s = one billion bytes per second) PC133 is [[backward compatible]] with PC100 and PC66.

=== {{Anchor|DDR1}} DDR ===
{{Main|DDR SDRAM}}

While the access latency of DRAM is fundamentally limited by the DRAM array, DRAM has very high potential bandwidth because each internal read is actually a row of many thousands of bits. To make more of this bandwidth available to users, a [[double data rate]] interface was developed. This uses the same commands, accepted once per cycle, but reads or writes two words of data per clock cycle. The DDR interface accomplishes this by reading and writing data on both the rising and falling edges of the clock signal. In addition, some minor changes to the SDR interface timing were made in hindsight, and the supply voltage was reduced from 3.3 to 2.5&nbsp;V. As a result, DDR SDRAM is not backwards compatible with SDR SDRAM.

DDR SDRAM (sometimes called ''DDR1'' for greater clarity) doubles the minimum read or write unit; every access refers to at least two consecutive words.

Typical DDR SDRAM clock rates are 133, 166 and 200&nbsp;MHz (7.5, 6, and 5 ns/cycle), generally described as DDR-266, DDR-333 and DDR-400 (3.75, 3, and 2.5&nbsp;ns per beat). Corresponding 184-pin DIMMs are known as PC-2100, PC-2700 and PC-3200. Performance up to DDR-550 (PC-4400) is available.

=== DDR2 ===
{{Main|DDR2 SDRAM}}

DDR2 SDRAM is very similar to DDR SDRAM, but doubles the minimum read or write unit again, to four consecutive words. The bus protocol was also simplified to allow higher performance operation. (In particular, the "burst terminate" command is deleted.) This allows the bus rate of the SDRAM to be doubled without increasing the clock rate of internal RAM operations; instead, internal operations are performed in units four times as wide as SDRAM. Also, an extra bank address pin (BA2) was added to allow eight banks on large RAM chips.

Typical DDR2 SDRAM clock rates are 200, 266, 333 or 400&nbsp;MHz (periods of 5, 3.75, 3 and 2.5&nbsp;ns), generally described as DDR2-400, DDR2-533, DDR2-667 and DDR2-800 (periods of 2.5, 1.875, 1.5 and 1.25&nbsp;ns). Corresponding 240-pin DIMMs are known as PC2-3200 through PC2-6400. DDR2 SDRAM is now available at a clock rate of 533&nbsp;MHz generally described as DDR2-1066 and the corresponding DIMMs are known as PC2-8500 (also named PC2-8600 depending on the manufacturer). Performance up to DDR2-1250 (PC2-10000) is available.

Note that because internal operations are at 1/2 the clock rate, DDR2-400 memory (internal clock rate 100&nbsp;MHz) has somewhat higher latency than DDR-400 (internal clock rate 200&nbsp;MHz).

=== DDR3 ===
{{Main|DDR3 SDRAM}}

DDR3 continues the trend, doubling the minimum read or write unit to eight consecutive words. This allows another doubling of bandwidth and external bus rate without having to change the clock rate of internal operations, just the width. To maintain 800–1600&nbsp;M transfers/s (both edges of a 400–800&nbsp;MHz clock), the internal RAM array has to perform 100–200&nbsp;M fetches per second.

Again, with every doubling, the downside is the increased [[Latency (engineering)|latency]]. As with all DDR SDRAM generations, commands are still restricted to one clock edge and command latencies are given in terms of clock cycles, which are half the speed of the usually quoted transfer rate (a [[CAS latency]] of 8 with DDR3-800 is 8/(400&nbsp;MHz) = 20 ns, exactly the same latency of CAS2 on PC100 SDR SDRAM).

DDR3 memory chips are being made commercially,<ref>{{cite web|url=http://www.simmtester.com/page/news/showpubnews.asp?num=145|title=What is DDR memory?}}</ref> and computer systems using them were available from the second half of 2007,<ref>{{cite news|url=http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/|title=Pipe Dreams: Six P35-DDR3 Motherboards Compared |date=June 5, 2007 |author=Thomas Soderstrom |newspaper=Tom's Hardware}}</ref> with significant usage from 2008 onwards.<ref>{{cite web|url=http://news.softpedia.com/news/AMD-to-Adopt-DDR3-in-Three-Years-13486.shtml|title=AMD to Adopt DDR3 in Three Years|date=28 November 2005}}</ref> Initial clock rates were 400 and 533&nbsp;MHz, which are described as DDR3-800 and DDR3-1066 (PC3-6400 and PC3-8500 modules), but 667 and 800&nbsp;MHz, described as DDR3-1333 and DDR3-1600 (PC3-10600 and PC3-12800 modules) are now common.<ref>{{cite web|url=http://www.anandtech.com/printarticle.aspx?i=3045|title=Super Talent & TEAM: DDR3-1600 Is Here! |date=July 20, 2007 |author=Wesly Fink |publisher=Anandtech}}</ref> Performance up to DDR3-2800 (PC3 22400 modules) are available.<ref>{{cite web |url=http://hothardware.com/News/GSKILL-Announces-DDR3-Memory-Kit-For-Ivy-Bridge/ |title=G.SKILL Announces DDR3 Memory Kit For Ivy Bridge |date=24 April 2012 |author=Jennifer Johnson}}</ref>

=== DDR4 ===
{{Main|DDR4 SDRAM}}

DDR4 SDRAM is the successor to [[DDR3 SDRAM]]. It was revealed at the [[Intel Developer Forum]] in San Francisco in 2008, and was due to be released to market during 2011. The timing varied considerably during its development - it was originally expected to be released in 2012,<ref>[http://intel.wingateweb.com/US08/published/sessions/MASS006/SF08_MASS006_100s.pdf DDR4 PDF page 23]</ref> and later (during 2010) expected to be released in 2015,<ref>{{cite web|url=http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/|title=DDR4 not expected until 2015|work=semiaccurate.com|date=16 August 2010}}</ref> before samples were announced in early 2011 and manufacturers began to announce that commercial production and release to market was anticipated in 2012. DDR4 reached mass market adoption around 2015, which is comparable with the approximately five years taken for DDR3 to achieve mass market transition over DDR2.

The DDR4 chips run at 1.2&nbsp;[[Volt|V]] or less,<ref>{{cite web|url=http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html|title=IDF: "DDR3 won't catch up with DDR2 during 2009"|work=Alphr}}</ref><ref>{{cite web|url=http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367|title=heise online - IT-News, Nachrichten und Hintergründe|work=heise online}}</ref> compared to the 1.5&nbsp;V of DDR3 chips, and have in excess of 2 billion [[data transfer]]s per second. They were expected to be introduced at frequency rates of 2133&nbsp;MHz, estimated to rise to a potential 4266&nbsp;MHz<ref>{{cite web |url=http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |title=Next-Generation DDR4 Memory to Reach 4.266GHz - Report |date=August 16, 2010 |publisher=Xbitlabs.com |access-date=2011-01-03 |url-status=dead |archive-url=https://web.archive.org/web/20101219085440/http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html |archive-date=December 19, 2010 }}</ref> and lowered voltage of 1.05&nbsp;V<ref>{{cite news|url=http://www.hardware-infos.com/news.php?news=2332|title=IDF: DDR4 memory targeted for 2012|publisher=hardware-infos.com|language=de|access-date=2009-06-16|archive-url=https://web.archive.org/web/20090713025046/http://www.hardware-infos.com/news.php?news=2332|archive-date=2009-07-13|url-status=dead}}</ref> by 2013.

DDR4 did ''not'' double the internal prefetch width again, but uses the same 8''n'' prefetch as DDR3.<ref name="jedec_ddr3_ddr4">{{cite press release |url=http://www.jedec.org/news/pressreleases/jedec-announces-key-attributes-upcoming-ddr4-standard |title=JEDEC Announces Key Attributes of Upcoming DDR4 Standard |publisher=[[JEDEC]] |date=2011-08-22 |access-date=2011-01-06}}</ref> Thus, it will be necessary to interleave reads from several banks to keep the data bus busy.

In February 2009, [[Samsung]] validated 40&nbsp;nm DRAM chips, considered a "significant step" towards DDR4 development<ref>{{cite news |url=http://www.tgdaily.com/content/view/41316/139/ |title=Samsung hints to DDR4 with first validated 40&nbsp;nm DRAM |last=Gruener |first=Wolfgang |date=February 4, 2009 |publisher=tgdaily.com |access-date=2009-06-16 |url-status=dead |archive-url=https://web.archive.org/web/20090524133306/http://www.tgdaily.com/content/view/41316/139/ |archive-date=May 24, 2009 }}</ref> since, as of 2009, current DRAM chips were only beginning to migrate to a 50&nbsp;nm process.<ref>{{cite web |url=http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |title=DDR3 Will be Cheaper, Faster in 2009 |last=Jansen |first=Ng |date=January 20, 2009 |publisher=dailytech.com |access-date=2009-06-17 |url-status=dead |archive-url=https://web.archive.org/web/20090622084614/http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm |archive-date=June 22, 2009 }}</ref> In January 2011, [[Samsung]] announced the completion and release for testing of a 30&nbsp;nm 2048&nbsp;MB{{binpre}} DDR4 DRAM module. It has a maximum bandwidth of 2.13&nbsp;[[Gbit/s]] at 1.2&nbsp;V, uses [[pseudo open drain]] technology and draws 40% less power than an equivalent DDR3 module.<ref>{{cite web |title=Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology |url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202 |publisher=Samsung |access-date=2011-03-13 |date=2011-01-04}}</ref><ref>{{cite web |url=http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html |title=Samsung develops DDR4 memory, up to 40% more efficient |work=TechSpot|date=4 January 2011 }}</ref>

=== DDR5 ===
{{Main|DDR5 SDRAM}}

In March 2017, JEDEC announced a DDR5 standard is under development,<ref>{{cite press release |title=JEDEC DDR5 & NVDIMM-P Standards Under Development |url=https://www.jedec.org/news/pressreleases/jedec-ddr5-nvdimm-p-standards-under-development |date=30 March 2017 |publisher=[[JEDEC]]}}</ref> but provided no details except for the goals of doubling the bandwidth of DDR4, reducing power consumption, and publishing the standard in 2018. The standard was released on 14 July 2020.<ref name="anandtech-ddr5">{{cite web|url=https://www.anandtech.com/show/15912/ddr5-specification-released-setting-the-stage-for-ddr56400-and-beyond|title=DDR5 Memory Specification Released: Setting the Stage for DDR5-6400 And Beyond|last=Smith|first=Ryan|date=2020-07-14|website=AnandTech|access-date=2020-07-15}}</ref>