Open main menu
Home
Random
Recent changes
Special pages
Community portal
Preferences
About Wikipedia
Disclaimers
Incubator escapee wiki
Search
User menu
Talk
Dark mode
Contributions
Create account
Log in
Editing
Verilog
(section)
Warning:
You are not logged in. Your IP address will be publicly visible if you make any edits. If you
log in
or
create an account
, your edits will be attributed to your username, along with other benefits.
Anti-spam check. Do
not
fill this in!
==Four-valued logic== The IEEE 1364 standard defines a [[four-valued logic]] with four states: 0, 1, Z ([[high impedance]]), and X (unknown logic value). For the competing VHDL, a dedicated standard for multi-valued logic exists as [[IEEE 1164]] with nine levels.<ref>{{cite book|first1=D. Michael |last1=Miller|first2=Mitchell A. |last2=Thornton|title=Multiple valued logic: concepts and representations|year=2008|publisher=Morgan & Claypool |isbn=978-1-59829-190-2|series=Synthesis Lectures on Digital Circuits and Systems|volume=12}}</ref>
Edit summary
(Briefly describe your changes)
By publishing changes, you agree to the
Terms of Use
, and you irrevocably agree to release your contribution under the
CC BY-SA 4.0 License
and the
GFDL
. You agree that a hyperlink or URL is sufficient attribution under the Creative Commons license.
Cancel
Editing help
(opens in new window)