Editing Branch predictor (section)

===Indirect branch predictor===
An [[indirect branch|indirect jump]] instruction can choose among more than two branches. Some processors have specialized indirect branch predictors.<ref>{{cite web |url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438h/BABEHAJJ.html |title=Cortex-A15 MPCore Technical Reference Manual, section 6.5.3 "Indirect predictor" |website=[[ARM Holdings]]}}</ref><ref>{{cite web |url=http://hoelzle.org/publications/TRCS97-10.pdf |title=Limits of Indirect Branch Prediction |author-first1=Karel |author-last1=Driesen |author-first2=Urs |author-last2=Hölzle |date=1997-06-25 |archive-url=https://web.archive.org/web/20160506213742/http://hoelzle.org/publications/TRCS97-10.pdf |archive-date=2016-05-06 |url-status=dead}}</ref> Newer processors from Intel<ref>{{cite web |url=https://arstechnica.com/features/2004/02/pentium-m/ |title=A Look at Centrino's Core: The Pentium M |author-first=Jon |author-last=Stokes |date=2004-02-25 |pages=2–3}}</ref> and AMD<ref>{{cite web |url=https://www.realworldtech.com/cpu-perf-analysis/5/ |title=Performance Analysis for Core 2 and K8: Part 1 |page=5 |date=2008-10-28 |author-first=Aaron |author-last=Kanter}}</ref> can predict indirect branches by using a two-level adaptive predictor. This kind of instruction contributes more than one bit to the history buffer. The [[IBM zEC12 (microprocessor)|zEC12]] and later [[z/Architecture]] processors from IBM support a {{Mono|BRANCH PREDICTION PRELOAD}} instruction that can preload the branch predictor entry for a given instruction with a branch target address constructed by adding the contents of a general-purpose register to an immediate displacement value.<ref>{{cite book |url=https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf |title=z/Architecture Principles of Operation |id=SA22-7832-13 |edition=Fourteenth |date=May 2022 |publisher=[[IBM]] |pages=7-42{{hyp}}7-45}}</ref><ref>{{cite web |url=https://www.redbooks.ibm.com/redbooks/pdfs/sg248138.pdf |title=IBM zEnterprise BC12 Technical Guide |date=February 2014 |page=78 |publisher=[[IBM]]}}</ref>

Processors without this mechanism will simply predict an indirect jump to go to the same target as it did last time.<ref name="Fog_Microarchitecture"/>