Editing Dynamic random-access memory (section)

====Folded bitline arrays====
The folded bitline array architecture routes bitlines in pairs throughout the array. The close proximity of the paired bitlines provide superior [[Common-mode signal|common-mode]] noise rejection characteristics over open bitline arrays. The folded bitline array architecture began appearing in DRAM ICs during the mid-1980s, beginning with the 256&nbsp;Kbit generation. This architecture is favored in modern DRAM ICs for its superior noise immunity.

This architecture is referred to as ''folded'' because it takes its basis from the open array architecture from the perspective of the circuit schematic. The folded array architecture appears to remove DRAM cells in alternate pairs (because two DRAM cells share a single bitline contact) from a column, then move the DRAM cells from an adjacent column into the voids.

The location where the bitline twists occupies additional area. To minimize area overhead, engineers select the simplest and most area-minimal twisting scheme that is able to reduce noise under the specified limit. As process technology improves to reduce minimum feature sizes, the signal to noise problem worsens, since coupling between adjacent metal wires is inversely proportional to their pitch. The array folding and bitline twisting schemes that are used must increase in complexity in order to maintain sufficient noise reduction. Schemes that have desirable noise immunity characteristics for a minimal impact in area is the topic of current research (Kenner, p.&nbsp;37).