Editing Integrated circuit (section)

=== ULSI, WSI, SoC and 3D-IC ===
{{Further|Wafer-scale integration|System on a chip|Three-dimensional integrated circuit}}
To reflect further growth of the complexity, the term ''ULSI'' that stands for "ultra-large-scale integration" was proposed for chips of more than 1 million transistors.<ref>{{cite journal|last1=Meindl|first1=J.D.|title=Ultra-large scale integration|journal=IEEE Transactions on Electron Devices|volume=31|issue=11|pages=1555–1561|doi=10.1109/T-ED.1984.21752|year=1984|bibcode=1984ITED...31.1555M|s2cid=19237178}}</ref>

[[Wafer-scale integration]] (WSI) is a means of building very large integrated circuits that uses an entire silicon wafer to produce a single "super-chip". Through a combination of large size and reduced packaging, WSI could lead to dramatically reduced costs for some systems, notably massively parallel supercomputers. The name is taken from the term Very-Large-Scale Integration, the current state of the art when WSI was being developed.<ref>{{cite patent|pubdate=1985|inventor-last1=Shanefield|inventor-first1=Daniel|title=Wafer scale integration|status=patent|country=US|number=4866501}}</ref><ref name= wsi2022 >{{cite web | last=Edwards | first=Benj | title=Hungry for AI? New supercomputer contains 16 dinner-plate-size chips | website=Ars Technica | date=2022-11-14 | url=https://arstechnica.com/information-technology/2022/11/hungry-for-ai-new-supercomputer-contains-16-dinner-plate-size-chips/ }}</ref>

A [[system-on-a-chip]] (SoC or SOC) is an integrated circuit in which all the components needed for a computer or other system are included on a single chip. The design of such a device can be complex and costly, and whilst performance benefits can be had from integrating all needed components on one die, the cost of licensing and developing a one-die machine still outweigh having separate devices. With appropriate licensing, these drawbacks are offset by lower manufacturing and assembly costs and by a greatly reduced power budget: because signals among the components are kept on-die, much less power is required (see [[#Packaging|Packaging]]).<ref>{{cite patent|inventor-last1=Klaas|inventor-first1=Jeff|title=System-on-a-chip|pubdate=2000|status=patent|country=US|number=6816750}}</ref> Further, signal sources and destinations are [[Locality of reference|physically closer]] on die, reducing the length of wiring and therefore [[Latency (engineering)|latency]], [[Data transmission|transmission]] power costs and [[waste heat]] from communication between modules on the same chip. This has led to an exploration of so-called [[Network on a chip|Network-on-Chip]] (NoC) devices, which apply system-on-chip design methodologies to digital communication networks as opposed to traditional [[Bus (computing)|bus architectures]].

A [[three-dimensional integrated circuit]] (3D-IC) has two or more layers of active electronic components that are integrated both vertically and horizontally into a single circuit. Communication between layers uses on-die signaling, so power consumption is much lower than in equivalent separate circuits. Judicious use of short vertical wires can substantially reduce overall wire length for faster operation.<ref>{{cite journal|last1=Topol|first1=A.W.|last2=Tulipe|first2=D.C.La|last3=Shi|first3=L|last4=et.|first4=al|title=Three-dimensional integrated circuits|journal=IBM Journal of Research and Development|volume=50|issue=4.5|pages=491–506|doi=10.1147/rd.504.0491|year=2006|s2cid=18432328}}</ref>