Editing Itanium (section)

==== Intel ====
The first generation of Itanium received no vendor-specific chipsets, only Intel's 460GX consisting of ten distinct chips. It supported up to four CPUs and 64 GB of memory at 4.2 GB/s, which is twice the system bus's bandwidth. Addresses and data were handled by two different chips. 460GX had an [[Accelerated Graphics Port|AGP]] X4 graphics bus, two 64-bit 66&nbsp;MHz [[Peripheral Component Interconnect|PCI]] buses and configurable 33&nbsp;MHz dual 32-bit or single 64-bit PCI bus(es).<ref>{{cite web |title=Intel 460GX Chipset Datasheet |url=http://developer.intel.com/design/itanium/downloads/24870301.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040723073549/http://developer.intel.com/design/itanium/downloads/24870301.pdf |archive-date=23 July 2004 |url-status=dead}}</ref>

There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E8870 chipset. It supports 128 GB of [[DDR SDRAM]] at 6.4 GB/s. It was originally designed for [[Rambus]] [[RDRAM]] [[serial communication|serial]] memory, but when RDRAM failed, Intel added four DDR SDRAM-to-RDRAM converter chips to the chipset.<ref>{{cite book |last1=Mueller |first1=Scott |last2=Soper |first2=Mark Edward |last3=Sosinsky |first3=Barrie |title=Upgrading and Repairing Servers |date=2006 |publisher=Pearson Education |isbn=0-13-279698-8 |url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT301 |access-date=6 April 2022}}</ref> When Intel had previously made such a converter for Pentium III chipsets 820 and 840, it drastically cut performance.<ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Intel's 820 Chipset - Performance using SDRAM |url=https://www.anandtech.com/show/465 |website=[[AnandTech]] |access-date=6 April 2022}}</ref><ref>{{cite web |last1=Shimpi |first1=Anand Lal |title=Rambus DRAM Part 2: Performance |url=https://www.anandtech.com/show/551 |website=[[AnandTech]] |access-date=6 April 2022}}</ref> E8870 provides eight 133&nbsp;MHz [[PCI-X]] buses (4.2 GB/s total because of bottlenecks) and a [[I/O Controller Hub#ICH4|ICH4]] hub with six [[USB 2.0]] ports.
Two E8870 can be linked together by two E8870SP Scalability Port Switches, each containing a 1MB (~200,000 cache lines) [[Bus snooping#Snoop filter|snoop filter]], to create an 8-socket system with double the memory and PCI-X capacity, but still only one ICH4. Further expansion to 16 sockets was planned.<ref>{{cite journal |display-authors=etal |last=Briggs |first=Fayé |title=Intel 870: a building block for cost-effective, scalable servers |journal=[[IEEE Micro]] |date=7 August 2002 |volume=22 |issue=2 (March–April) |pages=36–47 |doi=10.1109/MM.2002.997878 |citeseerx=10.1.1.140.2915 |s2cid=3201355 }}</ref><ref>{{cite web |title=Intel® E8870 Scalable Node Controller (SNC) Datasheet |url=http://www.intel.com/design/chipsets/datashts/25111203.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040701014149/http://www.intel.com/design/chipsets/datashts/25111203.pdf |archive-date=1 July 2004 |url-status=dead}}</ref><ref>{{cite web |title=Intel® E8870IO Server I/O Hub (SIOH) Datasheet |url=http://intel.com/design/chipsets/datashts/25111103.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20030706004227/http://intel.com/design/chipsets/datashts/25111103.pdf |archive-date=6 July 2003 |url-status=dead}}</ref> In 2004 Intel revealed plans for its next Itanium chipset, codenamed ''Bayshore'', to support [[PCI-e]] and [[DDR2 SDRAM|DDR2]] memory, but canceled it the same year.<ref>{{cite web |title=Intel Outlines Platform Innovations For More Manageable, Balanced And Secure Enterprise Computing |url=https://www.intel.com/pressroom/archive/releases/2004/20040218corp.htm |publisher=Intel |access-date=7 April 2022}}</ref><ref name="ibm_ditching_itanium"/>