Editing PIC microcontrollers (section)

==Core architecture==
The PIC architecture (excluding the unrelated PIC32 and PIC64) is a one-operand [[Accumulator machine#Accumulator machines|accumulator machine]] like the [[PDP-8]] or the [[Apollo Guidance Computer]]. Its characteristics are:

* One [[Accumulator (computing)|accumulator]] (W0), which is an implied operand of almost every instruction.
* A small number of fixed-length instructions, with mostly fixed timing (2 clock cycles, or 4 clock cycles in 8-bit models).
* A small amount of addressable data space (32, 128, or 256 bytes, depending on the family), extended through banking
* Separate code and data spaces ([[Harvard architecture]]).
* Instruction memory is wider than data memory, allowing immediate constants within an instruction. (This is a major difference from the other early accumulator machines mentioned above.)
* The second operand is a memory location ''or'' an immediate constant.
* There are no other [[addressing modes]], although an indirect address mode can be emulated using the indirect register(s).
* Data-space mapped CPU, port, and peripheral registers
** ALU status flags are mapped into the data space
** The program counter is also mapped into the data space and writeable (this is used to implement indirect jumps).
* A hardware stack for storing return addresses
* There are only unconditional branch instructions
* Conditional execution is achieved via conditional skip instructions, which conditionally nullify the following instruction.

There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as "the register file" or simply as "the registers".

===Data space (RAM)===
PICs have a set of registers that function as general-purpose RAM. Special-purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC device types have some [[Bank switching|banking mechanism]] to extend addressing to additional memory (but some device models have only one bank implemented). Later series of devices feature move instructions, which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move must be achieved through the accumulator.

To implement indirect addressing, a "file select register" (FSR) and "indirect register" (INDF) are used. A register number is written to the FSR, after which reads from or writes to INDF will actually be from or to the register pointed to by FSR. Later devices extended this concept with post- and pre- increment/decrement for greater efficiency in accessing sequentially stored data. This also allows FSR to be treated almost like a stack pointer (SP).

External data memory is not directly addressable except in some PIC18 devices with high pin count. However, general I/O ports can be used to implement a parallel bus or a serial interface for accessing external memory and other peripherals (using subroutines), with the caveat that such programmed memory access is (of course) much slower than access to the native memory of the PIC MCU.

===Code space===
The code space is generally implemented as on-chip [[Read-only memory|ROM]], [[EPROM]] or [[flash ROM]]. In general, there is no provision for storing code in external memory due to the lack of an external memory interface. The exceptions are PIC17 and select high pin count PIC18 devices.<ref>{{cite web |title=AN869: External Memory Interfacing Techniques for the PIC18F8XXX |url=http://ww1.microchip.com/downloads/en/AppNotes/00869b.pdf |first=Tim |last=Rovnak |publisher=Microchip Technology |year=2003 |id=DS00869B |access-date=24 August 2009}}</ref>

===Word size===
All PICs handle (and address) data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space. For example, PICs in the baseline (PIC12) and mid-range (PIC16) families have program memory addressable in the same wordsize as the instruction width, i.e. 12 or 14 bits respectively. In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments (bytes), which differs from the instruction width of 16 bits.

In order to be clear, the program memory capacity is usually stated in number of (single-word) instructions, rather than in bytes.

===Stacks===
PICs have a hardware [[call stack]], which is used to save return addresses. The hardware stack is not software-accessible on earlier devices, but this changed with the PIC18 series devices.

Hardware support for a general-purpose parameter stack was lacking in early series, but this greatly improved in the PIC18 series, making the PIC18 series architecture more friendly to high-level language compilers.

===Instruction set===
{{Further|PIC instruction listings}}
PIC instruction sets vary from about 35 instructions for the low-end PICs to over 80 instructions for the high-end PICs. The instruction set includes instructions to perform a variety of operations on registers directly, on the [[Accumulator (computing)|accumulator]] and a literal constant, or on the accumulator and a [[Processor register|register]], as well as for conditional execution, and program branching.

A few operations, such as bit setting and testing, can be performed on any numbered register, but 2-input arithmetic operations always involve W (the accumulator), writing the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register. On the older cores, all register moves needed to pass through W, but this changed on the "high-end" cores.

PIC cores have skip instructions, which are used for conditional execution and branching. The skip instructions are "skip if bit set" and "skip if bit not set". Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip (with the opposite condition) followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction. It is possible to skip skip instructions. For example, the instruction sequence "skip if A; skip if B; C" will execute C if A is true or if B is false.

The PIC18 series implemented shadow registers: these are registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.

In general, PIC instructions fall into five classes:

* Operation on working register (WREG) with 8-bit immediate ("literal") operand. E.g. <code>movlw</code> (move literal to WREG), <code>andlw</code> (AND literal with WREG). One instruction peculiar to the PIC is <code>retlw</code>, load immediate into WREG and return, which is used with computed [[branch (computer science)|branch]]es to produce [[lookup table]]s.
* Operation with WREG and indexed register. The result can be written to either the working register (e.g. <code>addwf ''reg'',w</code>). or the selected register (e.g. <code>addwf ''reg'',f</code>).
* Bit operations. These take a register number and a bit number, and perform one of 4 actions: set or clear a bit, and test and skip on set/clear. The latter are used to perform conditional branches. The usual ALU status flags are available in a numbered register so operations such as "branch on carry clear" are possible.
* Control transfers. Other than the skip instructions previously mentioned, there are only two: <code>goto</code> and <code>call</code>.
* A few miscellaneous zero-operand instructions, such as return from subroutine, and <code>sleep</code> to enter low-power mode.

===Performance===
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs{{Citation needed|date=August 2010}} and is still among the simplest and cheapest. The Harvard architecture, in which instructions and data come from separate sources, simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption.

The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated by the relatively large program space of the PIC (e.g. 4096 × 14-bit words on the 16F690) and by the design of the instruction set, which allows embedded constants. For example, a branch instruction's target may be indexed by W, and execute a "RETLW", which does as it is named{{snd}} return with literal in W.

Interrupt latency is constant at three instruction cycles. External interrupts have to be synchronized with the four-clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt-driven low-jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.

===Advantages===
* Small instruction set to learn
* [[Reduced instruction set computer|RISC]] architecture
* Built-in oscillator with selectable speeds
* Easy entry level, in-circuit programming plus in-circuit debugging [[PICkit]] units available for less than $50
* Inexpensive microcontrollers
* Wide range of interfaces including [[I²C]], [[Serial Peripheral Interface Bus|SPI]], [[USB]], [[Universal asynchronous receiver/transmitter|UART]], [[Analog-to-digital converter|A/D]], programmable comparators, [[Pulse-width modulation|PWM]], [[Local Interconnect Network|LIN]], [[Controller area network|CAN]], [[Parallel slave port|PSP]], and Ethernet<ref>{{cite web |url=http://www.microchip.com/maps/Microcontroller.aspx |title=Microchip Advanced Part Selector |publisher=Microchip |archive-url=https://web.archive.org/web/20160110012820/http://www.microchip.com/maps/Microcontroller.aspx |archive-date=2016-01-10 |access-date=2022-12-14}}</ref>
* Availability of processors in [[Dual in-line package|DIL]] package makes them easy to handle for hobby use.

===Limitations===
* One [[Accumulator (computing)|accumulator]]
* Register-[[bank switching]] is required to access the entire RAM of many devices
* Operations and registers are not [[Orthogonal#Computer science|orthogonal]]; some instructions can address RAM and/or [[constant (computer science)|immediate]] constants, while others can use the accumulator only.

The following stack limitations have been addressed in the '''PIC18''' series, but still apply to earlier cores:

* The hardware call stack is not addressable, so preemptive [[computer multitasking|task switching]] cannot be implemented
* Software-implemented [[stack (data structure)|stack]]s are not efficient, so it is difficult to generate [[Reentrant (subroutine)|reentrant]] code and support [[local variable]]s

With paged program memory, there are two page sizes to worry about: one for CALL and GOTO and another for computed GOTO (typically used for table lookups). For example, on PIC16, CALL and GOTO have 11 bits of addressing, so the page size is 2048 instruction words. For computed GOTOs, where you add to PCL, the page size is 256 instruction words. In both cases, the upper address bits are provided by the PCLATH register. This register must be changed every time control transfers between pages. PCLATH must also be preserved by any interrupt handler.<ref>{{cite web|url=http://massmind.org/techref/microchip/pages.htm|title=Slowing 208.80.153.50,10-192-48-43&c=1&t=43197.5553483796|website=massmind.org|access-date=7 April 2018}}</ref>

===Compiler development===
While several commercial compilers are available, in 2008, Microchip released their own C compilers, C18 and C30, for the line of 18F 24F and 30/33F processors.

As of 2013, Microchip offers their XC series of compilers, for use with [[MPLAB|MPLAB X]]. Microchip will eventually phase out its older compilers, such as C18, and recommends using their XC series compilers for new designs.<ref>{{cite web|url=http://www.microchip.com/pagehandler/en_us/devtools/mplabxc/|title=MPLAB® XC: Compiler Solutions|website=microchip.com|access-date=7 April 2018}}</ref>

The RISC instruction set of the PIC assembly language code can make the overall flow difficult to comprehend. Judicious use of simple [[macro (computer science)|macros]] can increase the readability of PIC assembly language. For example, the original [[Parallax, Inc. (company)|Parallax]] PIC assembler ("SPASM") has macros, which hide W and make the PIC look like a two-address machine. It has macro instructions like <code>mov b, a</code> (move the data from address ''a'' to address ''b'') and <code>add b, a</code> (add data from address ''a'' to data in address ''b''). It also hides the skip instructions by providing three-operand branch macro instructions, such as <code>cjne a, b, dest</code> (compare ''a'' with ''b'' and jump to ''dest'' if they are not equal).