Editing Static random-access memory (section)

==SRAM operation==
{{how-to|section|date=January 2023}}
An SRAM cell has three states:

* '''Standby:''' The circuit is idle.
* '''Reading:''' The data has been requested.
* '''Writing:''' Updating the contents.

SRAM operating in read and write modes should have ''readability'' and ''write stability'', respectively. The three different states work as follows:

===Standby===
If the word line is not asserted, the ''access'' transistors M<sub>5</sub> and M<sub>6</sub> disconnect the cell from the bit lines. The two cross-coupled inverters formed by M<sub>1</sub>{{snd}}M<sub>4</sub> will continue to reinforce each other as long as they are connected to the supply.

===Reading===
In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a single access transistor and bit line, e.g. M<sub>6</sub>, BL. However, bit lines are relatively long and have large [[parasitic capacitance]]. To speed up reading, a more complex process is used in practice: The read cycle is started by precharging both bit lines BL and <span style="text-decoration: overline;">BL</span>, to high (logic '''1''') voltage. Then asserting the word line WL enables both the access transistors M<sub>5</sub> and M<sub>6</sub>, which causes one bit line BL voltage to slightly drop. Then the BL and <span style="text-decoration: overline;">BL</span> lines will have a small voltage difference between them. A sense amplifier will sense which line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read operation. As the NMOS is more powerful, the pull-down is easier. Therefore, bit lines are traditionally precharged to high voltage. Many researchers are also trying to precharge at a slightly low voltage to reduce the power consumption.<ref>{{Cite journal|url=https://www.tandfonline.com/doi/full/10.1080/1023697X.2014.970761|title=SRAM precharge system for reducing write power|first1=Hussain Mohammed Dipu|last1=Kabir|first2=Mansun|last2=Chan|date=January 2, 2015|journal=HKIE Transactions|volume=22|issue=1|pages=1–8|via=CrossRef|doi=10.1080/1023697X.2014.970761|s2cid=108574841 |url-access=subscription}}</ref><ref>{{Cite web|url=https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.119.3735|title=CiteSeerX|website=CiteSeerX|citeseerx=10.1.1.119.3735 }}</ref>

===Writing===
The write cycle begins by applying the value to be written to the bit lines. To write a 0, a 0 is applied to the bit lines, such as setting <span style="text-decoration: overline;">BL</span> to 1 and BL to 0. This is similar to applying a reset pulse to an [[Latch (electronic)|SR-latch]], which causes the flip flop to change state. A '''1''' is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. This works because the bit line input-drivers are designed to be much stronger than the relatively weak transistors in the cell itself so they can easily override the previous state of the cross-coupled inverters. In practice, access NMOS transistors M<sub>5</sub> and M<sub>6</sub> have to be stronger than either bottom NMOS (M<sub>1</sub>, M<sub>3</sub>) or top PMOS (M<sub>2</sub>, M<sub>4</sub>) transistors. This is easily obtained as PMOS transistors are much weaker than NMOS when same sized. Consequently, when one transistor pair (e.g.  M<sub>3</sub> and M<sub>4</sub>) is only slightly overridden by the write process, the opposite transistors pair (M<sub>1</sub> and M<sub>2</sub>) gate voltage is also changed. This means that the M<sub>1</sub> and M<sub>2</sub> transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing process.

===Bus behavior===
[[RAM]] with an access time of 70&nbsp;ns will output valid data within 70&nbsp;ns from the time that the address lines are valid. Some SRAM cells have a ''page mode'', where words of a page (256, 512, or 1024 words) can be read sequentially with a significantly shorter access time (typically approximately 30&nbsp;ns). The page is selected by setting the upper address lines and then words are sequentially read by stepping through the lower address lines.