Editing Addressing mode (section)

==Other addressing modes for code or data==

===Absolute/direct===
    +------+-----+--------------------------------------+
    | load | reg |         address                      |
    +------+-----+--------------------------------------+
 
    (Effective address = address as given in instruction)

This requires space in an instruction for quite a large address. It is often available on CISC machines which have variable-length instructions, such as [[x86]].

Some RISC machines have a special ''Load Upper Literal'' instruction which places a 16- or 20-bit constant in the top half of a register.  That can then be used as the base register in a base-plus-offset addressing mode which supplies the low-order 16 or 12 bits.  The combination allows a full 32-bit address.

===Indexed absolute===
    +------+-----+-----+--------------------------------+
    | load | reg |index|         address                |
    +------+-----+-----+--------------------------------+
 
    (Effective address = address + contents of specified index register)

This also requires space in an instruction for quite a large address. The address could be the start of an array or vector, and the index could select the particular array element required. The processor may scale the index register to allow for the [[stride of an array|size of each array element]].

Note that this is more or less the same as base-plus-offset addressing mode, except that the offset in this case is large enough to address any memory location.

''Example 1'':
Within a subroutine, a programmer may define a string as a local constant or a [[static variable]]. The address of the string is stored in the literal address in the instruction. The offset—which character of the string to use on this iteration of a loop—is stored in the index register.

''Example 2'':
A programmer may define several large arrays as globals or as [[field (computer science)|class variables]]. The start of the array is stored in the literal address (perhaps modified at program-load time by a [[relocating loader]]) of the instruction that references it. The offset—which item from the array to use on this iteration of a loop—is stored in the index register. Often the instructions in a loop re-use the same register for the loop counter and the offsets of several arrays.

===Base plus index===
    +------+-----+-----+-----+
    | load | reg | base|index|
    +------+-----+-----+-----+
 
    (Effective address = contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector, and the index could select the particular array element required. The processor may scale the [[index register]] to allow for the [[stride of an array|size of each array element]]. This could be used for accessing elements of an array passed as a parameter.

===Base plus index plus offset===
    +------+-----+-----+-----+----------------+
    | load | reg | base|index|     offset     |
    +------+-----+-----+-----+----------------+
 
    (Effective address = offset + contents of specified base register + contents of specified index register)

The base register could contain the start address of an array or vector of records, the index could select the particular record required, and the offset could select a field within that record. The processor may scale the index register to allow for the [[stride of an array|size of each array element]].

===Scaled===
    +------+-----+-----+-----+
    | load | reg | base|index|
    +------+-----+-----+-----+
 
    (Effective address = contents of specified base register + scaled contents of specified index register)

The base register could contain the start address of an array or [[vector data structure]], and the index could contain the offset of the one particular array element required.

This addressing mode dynamically scales the value in the index register to allow for the size of each array element, e.g. if the array elements are double precision floating-point numbers occupying 8 bytes each then the value in the index register is multiplied by 8 before being used in the effective address calculation. The scale factor is normally restricted to being a [[power of two]], so that [[bit shift|shifting]] rather than multiplication can be used.

===Register indirect===
    +------+------+-----+
    | load | reg1 | base|
    +------+------+-----+
  
    (Effective address = contents of base register)

A few computers have this as a distinct addressing mode. Many computers just use ''base plus offset'' with an offset value of 0. For example, (A7)

===Register autoincrement indirect===
    +------+-----+-------+
    | load | reg | base  |
    +------+-----+-------+
 
    (Effective address = contents of base register)

After determining the effective address, the value in the base register is incremented by the size of the data item that is to be accessed. For example, (A7)+ would access the content of the address register A7, then increase the address pointer of A7 by 1 (usually 1 word). Within a loop, this addressing mode can be used to step through all the elements of an array or vector.

In high-level languages it is often thought to be a good idea that functions which return a result should not have [[side effect (computer science)|side effects]] (lack of side effects makes program understanding and validation much easier). This addressing mode has a side effect in that the base register is altered. If the subsequent memory access causes an error (e.g. page fault, bus error, address error) leading to an interrupt, then restarting the instruction becomes much more problematic since one or more registers may need to be set back to the state they were in before the instruction originally started.

There have been at least three computer architectures that have had implementation problems with regard to recovery from faults when this addressing mode is used:
*[[Digital Equipment Corporation|DEC]] [[PDP-11]]. Could have one or two autoincrement register operands.<ref>{{cite book |url=http://www.bitsavers.org/pdf/dec/pdp11/handbooks/EB-23657-18_PDP-11_Architecture_Handbook_1983.pdf |title=PDP-11 Architecture Handbook |publisher=[[Digital Equipment Corporation]] |date=1973}}</ref> Some models, such as the PDP-11/45 and PDP-11/70, had a register that recorded modifications to registers, allowing the fault handler to undo the register modifications and re-execute the instruction.<ref>{{cite book |url=http://www.bitsavers.org/pdf/dec/pdp11/handbooks/PDP-1145_Handbook_1973.pdf |title=PDP-11/45 Processor Handbook |pages=150–153 |publisher=[[Digital Equipment Corporation]] |date=1973}}</ref>
*[[Motorola 68000 series]]. Could have one or two autoincrement register operands.<ref>{{cite book |url=http://bitsavers.org/components/motorola/68000/M68000PM_AD_Rev_1_Programmers_Reference_Manual_1992.pdf |title=M68000 Family Programmer's Reference Manual |publisher=[[Motorola]] |date=1992}}</ref> The [[68010]] and later processors resolved the problem by saving the processor's internal state on [[bus error|bus]] or address errors and restoring it when returning from the fault.<ref>{{cite book |url=http://bitsavers.org/components/motorola/68000/MC68010_68012_Data_Sheet_May85.pdf |title=MC68010/MC68012 16-/32-Bit Virtual Memory Microprocessors |pages=5{{hyp}}12-5{{hyp}}15 |publisher=[[Motorola]] |date=May 1985}}</ref><ref>{{cite book |url=http://bitsavers.org/components/motorola/68000/MC68020_32-Bit_Microprocessor_Users_Manual_1984.pdf |title=MC68020 32-Bit Microprocessor User's Manual |pages=6{{hyp}}9-6{{hyp}}10 |publisher=[[Prentice-Hall]] |date=1984 |isbn=0-13-541418-0}}</ref><ref>{{cite book |url=http://bitsavers.org/components/motorola/68000/MC68030_Users_Manual_3ed_1990.pdf |title=MC68030 Enhanced 32-Bit Microprocessor User's Manual |edition=Third |pages=8{{hyp}}7-8{{hyp}}8 |publisher=[[Prentice-Hall]] |date=1990 |isbn=0-13-566423-3}}</ref><ref>{{cite book |url=http://bitsavers.org/components/motorola/68000/MC68040_Users_Manual_1989.pdf |title=MC68040 32-Bit Microprocessor User's Manual |edition=Third |pages=9{{hyp}}8-9{{hyp}}9 |publisher=[[Motorola]] |date=1989}}</ref>
*DEC [[VAX]]. Could have up to 6 autoincrement register operands. The First Part Done bit in the saved [[status register|processor status longword]] in a stack frame for a fault is set if the faulting instruction must not be restarted at the beginning, resolving the problem.<ref>{{cite book |url=http://www.bitsavers.org/pdf/dec/vax/archSpec/EY-3459E-DP_VAX_Architecture_Reference_Manual_1987.pdf |title=VAX Architecture Reference Manual |page=21 |publisher=[[Digital Equipment Corporation]] |date=1987 |isbn=0-932376-86-X}}</ref>

===Register autodecrement indirect===
    +------+-----+-----+
    | load | reg | base|
    +------+-----+-----+
 
    (Effective address = new contents of base register)

Before determining the effective address, the value in the base register is decremented by the size of the data item which is to be accessed.

Within a loop, this addressing mode can be used to step backwards through all the elements of an array or vector. A stack can be implemented by using this mode in conjunction with the previous addressing mode (autoincrement).

See the discussion of side-effects under the [[#Register autoincrement indirect|autoincrement addressing mode]].

===Memory indirect or deferred===
Any of the addressing modes mentioned in this article could have an extra bit to indicate indirect addressing, i.e. the address calculated using some mode is in fact the address of a location (typically a complete [[word (data type)|word]]) which contains the actual effective address. On some machines the indirect word could indicate indexing, indirection, tallying{{efn|Either increment or decrement.}} or some combination.

Indirect addressing may be used for code or data. It can make implementation of ''pointers'', ''references'', or ''[[handle (computing)|handle]]s'' much easier, and can also make it easier to call subroutines which are not otherwise addressable. Indirect addressing does carry a performance penalty due to the extra memory access involved.

Some early minicomputers (e.g. DEC [[PDP-8]], [[Data General Nova]]) had only a few registers and only a limited direct addressing range (8 bits). Hence the use of memory indirect addressing was almost the only way of referring to any significant amount of memory.

Half of the [[PDP-11 architecture|DEC PDP-11]]'s eight addressing modes are deferred. Register deferred @Rn is the same as register indirect as defined above. Predecrement deferred @-(Rn), postincrement deferred @(Rn)+, and indexed deferred @nn(Rn) modes point to addresses in memory which are read to find the address of the parameter. The PDP-11's deferred mode, when combined with the program counter, provide its absolute addressing mode.

===PC-relative===
    +------+------+---------+----------------+
    | load | reg1 | base=PC |     offset     |
    +------+------+---------+----------------+
 
    reg1 := RAM[PC + offset]
    (Effective address = PC + offset)

The PC-relative addressing mode can be used to load a register with a value stored in program memory a short distance away from the current instruction. It can be seen as a special case of the "base plus offset" addressing mode, one that selects the program counter (PC) as the "base register".

There are a few CPUs that support PC-relative data references. Such CPUs include:

The [[x86-64]] architecture and the 64-bit [[ARMv8-A]] architecture<ref>{{cite web|url=https://quequero.org/2014/04/introduction-to-arm-architecture/|title=Introduction to ARMv8 64-bit Architecture|date = 9 April 2014|work = UIC Academy |publisher = quequero.org}}</ref> have PC-relative addressing modes, called "RIP-relative" in x86-64 and "literal" in ARMv8-A.  The [[Motorola 6809]] also supports a PC-relative addressing mode.

The [[PDP-11]] architecture, the [[VAX]] architecture, and the 32-bit [[ARM architecture]]s support PC-relative addressing by having the PC in the register file.

The [[IBM]] [[z/Architecture]] includes specific instructions, e.g., Load Relative Long, with PC-relative addressing if the General-Instructions-Extension Facility is active.

When this addressing mode is used, the compiler typically places the constants in a [[literal pool]] immediately before or immediately after the subroutine that uses them, to prevent accidentally executing those constants as instructions.

This addressing mode, which always fetches data from memory or stores data to memory and then sequentially falls through to execute the next instruction (the effective address points to data), should not be confused with "PC-relative branch" which does not fetch data from or store data to memory, but instead branches to some other instruction at the given offset (the effective address points to an executable instruction).