Editing CPU cache (section)

===Example===
The original [[Pentium 4]] processor had a four-way set associative L1 data cache of 8&nbsp;[[Kibibyte|KiB]] in size, with 64-byte cache blocks. Hence, there are 8&nbsp;KiB&nbsp;/&nbsp;64&nbsp;=&nbsp;128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128&nbsp;/&nbsp;4&nbsp;=&nbsp;32 sets, and hence 2<sup>5</sup>&nbsp;=&nbsp;32 different indices. There are 2<sup>6</sup>&nbsp;=&nbsp;64 possible offsets. Since the CPU address is 32 bits wide, this implies 32&nbsp;&minus;&nbsp;5&nbsp;&minus;&nbsp;6&nbsp;=&nbsp;21 bits for the tag field.

The original Pentium&nbsp;4 processor also had an eight-way set associative L2 integrated cache 256&nbsp;KiB in size, with 128-byte cache blocks. This implies 32&nbsp;&minus;&nbsp;8&nbsp;&minus;&nbsp;7&nbsp;=&nbsp;17 bits for the tag field.<ref name="ccs.neu.edu" />