Editing MOS Technology 6502 (section)

==Detailed behavior==
[[Image:BreakNES MOS 6502.jpg|right|thumb|6502 processor die with drawn-in NMOS transistors and labels hinting at the functionality of the 6502's components]]
{{See also|Interrupts in 65xx processors}}
The processor's [[non-maskable interrupt]] (NMI) input is [[Interrupt#Edge-triggered|edge sensitive]], which means that the interrupt is triggered by the falling edge of the signal rather than its level. The implication of this feature is that a [[wired-OR]] interrupt circuit is not readily supported. However, this also prevents nested NMI interrupts from occurring until the hardware makes the NMI input inactive again, often under control of the NMI [[interrupt handler]].

The simultaneous assertion of the NMI and [[Interrupt request|IRQ]] (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will almost immediately respond to IRQ, as IRQ is [[Interrupt#Level-triggered|level sensitive]]. Thus a sort of built-in interrupt priority was established in the 6502 design. (The first opcode of the NMI handler is executed before the IRQ is detected again.)

{{anchor|BRK Flag}}The B flag is set by the 6502's periodically sampling its NMI edge detector's output and its IRQ input. The IRQ signal being driven low is only recognized though if IRQs are not masked by the I flag. If in this way a NMI request or (maskable) IRQ is detected the B flag is set to zero and causes the processor to execute the BRK instruction next instead of executing the next instruction based on the program counter.<ref>{{Cite book |url=https://github.com/emu-russia/breaks/releases/download/6502-book-revB5/Breaking_6502_Eng_B5.pdf |title=Breaking NES Book – 6502 Core |date=2022-06-24 |edition=B5 |pages=61–62 |quote=The arrival of any interrupt is reflected on flag B, the output of which (B_OUT) forces the processor to execute a BRK instruction ... |access-date=2023-12-24 |archive-date=2024-04-12 |archive-url=https://web.archive.org/web/20240412044616/https://github.com/emu-russia/breaks/releases/download/6502-book-revB5/Breaking_6502_Eng_B5.pdf |url-status=live }}</ref><ref>{{Cite web|title=6502 BRK and B bit|url=http://visual6502.org/wiki/index.php?title=6502_BRK_and_B_bit|url-status=dead|access-date=2021-05-15|website=VisualChips|archive-date=2021-04-05|archive-url=https://web.archive.org/web/20210405071302/http://visual6502.org/wiki/index.php?title=6502_BRK_and_B_bit}}</ref>

The BRK instruction then pushes the processor status onto the stack, with the B flag bit set to zero. At the end of its execution the BRK instruction resets the B flag's value to one. This is the only way the B flag can be modified. If an instruction other than the BRK instruction pushes the B flag onto the stack as part of the processor status<ref>{{Cite web|title=FLAGS|url=https://github.com/ogamespec/breaks/blob/master/Docs/6502/6502_circuitlab/flags.png|access-date=2021-05-15|website=ogamespec|quote=B_OUT; INTERNAL DATA BUS (DB)}}</ref> the B flag always has the value one.

A high-to-low transition on the SO input pin will set the processor's overflow status bit. This can be used for fast response to external hardware. For example, a high-speed [[Polling (computer science)|polling]] device driver can poll the hardware once in only three cycles using a Branch-on-oVerflow-Clear (<code>BVC</code>) instruction that branches to itself until overflow is set by an SO falling transition. The [[Commodore 1541]] and other [[Commodore International|Commodore]] [[floppy disk]] drives use this technique to detect when the [[serialization|serializer]] is ready to transfer another byte of disk data. The system hardware and software design must ensure that an SO will not occur during arithmetic processing and disrupt calculations.