Editing Operating system (section)

====Input/output====

=====Interrupt-driven I/O=====
{{Expand section|date=April 2022}}
When a [[user (computing)|computer user]] types a key on the keyboard, typically the character appears immediately on the screen. Likewise, when a user moves a [[computer mouse|mouse]], the [[Cursor (user interface)|cursor]] immediately moves across the screen. Each keystroke and mouse movement generates an ''interrupt'' called ''Interrupt-driven I/O''. An interrupt-driven I/O occurs when a process causes an interrupt for every character<ref name="sco-ch5-p294"/> or word<ref>{{cite book
 |title        = Users Handbook - PDP-7
 |id           = F-75
 |year         = 1965
 |url          = http://bitsavers.org/pdf/dec/pdp7/F-75_PDP-7userHbk_Jun65.pdf
 |section      = Program Interrupt Controller (PIC)
 |section-url  = http://bitsavers.org/pdf/dec/pdp7/F-75_PDP-7userHbk_Jun65.pdf#page=62
 |pages        = [http://bitsavers.org/pdf/dec/pdp7/F-75_PDP-7userHbk_Jun65.pdf#page=63 48]
 |publisher    = [[Digital Equipment Corporation]]
 |access-date  = April 20, 2022
 |archive-date = 10 May 2022
 |archive-url  = https://web.archive.org/web/20220510164742/http://bitsavers.org/pdf/dec/pdp7/F-75_PDP-7userHbk_Jun65.pdf
 |url-status   = live
}}</ref> transmitted.

=====Direct memory access=====
Devices such as [[hard disk drive]]s, [[solid-state drive]]s, and [[magnetic tape]] drives can transfer data at a rate high enough that interrupting the CPU for every byte or word transferred, and having the CPU transfer the byte or word between the device and memory, would require too much CPU time. Data is, instead, transferred between the device and memory independently of the CPU by hardware such as a [[channel I/O|channel]] or a [[direct memory access]] controller; an interrupt is delivered only when all the data is transferred.<ref>{{cite book|url=http://bitsavers.org/pdf/dec/pdp1/F25_PDP1_IO.pdf|title=PDP-1 Input-Output Systems Manual|publisher=[[Digital Equipment Corporation]]|pages=19–20|access-date=16 August 2022|archive-date=25 January 2019|archive-url=https://web.archive.org/web/20190125050839/http://bitsavers.org/pdf/dec/pdp1/F25_PDP1_IO.pdf|url-status=live}}</ref>

If a [[computer program]] executes a [[system call]] to perform a block I/O ''write'' operation, then the system call might execute the following instructions:
* Set the contents of the CPU's [[Processor register|registers]] (including the [[program counter]]) into the [[process control block]].<ref name="osc-ch2-p32_b">{{cite book
  | last = Silberschatz
  | first = Abraham
  | title = Operating System Concepts, Fourth Edition
  | publisher = Addison-Wesley
  | year = 1994
  | page = 32
  | isbn = 978-0-201-50480-4
}}</ref>
* Create an entry in the device-status table.<ref name="osc-ch2-p34">{{cite book
  | last = Silberschatz
  | first = Abraham
  | title = Operating System Concepts, Fourth Edition
  | publisher = Addison-Wesley
  | year = 1994
  | page = 34
  | isbn = 978-0-201-50480-4
}}</ref> The operating system maintains this table to keep track of which processes are waiting for which devices. One field in the table is the [[memory address]] of the process control block.
* Place all the characters to be sent to the device into a [[random-access memory|memory buffer]].<ref name="sco-ch5-p308_b"/>
* Set the memory address of the memory buffer to a predetermined device register.<ref name="sco-ch5-p295">{{cite book
  | last = Tanenbaum
  | first = Andrew S.
  | title = Structured Computer Organization, Third Edition
  | publisher = Prentice Hall
  | year = 1990
  | page = [https://archive.org/details/structuredcomput00tane/page/295 295]
  | isbn = 978-0-13-854662-5
  | url = https://archive.org/details/structuredcomput00tane/page/295
  }}</ref>
* Set the buffer size (an integer) to another predetermined register.<ref name="sco-ch5-p295"/>
* Execute the [[machine code|machine instruction]] to begin the writing.
* Perform a [[context switch]] to the next process in the [[multilevel feedback queue|ready queue]].

While the writing takes place, the operating system will context switch to other processes as normal. When the device finishes writing, the device will ''interrupt'' the currently running process by ''asserting'' an [[Interrupt request (PC architecture)|interrupt request]]. The device will also place an integer onto the data bus.<ref name="sco-ch5-p309">{{cite book
  | last = Tanenbaum
  | first = Andrew S.
  | title = Structured Computer Organization, Third Edition
  | publisher = Prentice Hall
  | year = 1990
  | page = [https://archive.org/details/structuredcomput00tane/page/309 309]
  | isbn = 978-0-13-854662-5
  | url = https://archive.org/details/structuredcomput00tane/page/309
  }}</ref> Upon accepting the interrupt request, the operating system will:
* Push the contents of the [[program counter]] (a register) followed by the [[status register]] onto the [[call stack]].<ref name="osc-ch2-p31"/>
* Push the contents of the other registers onto the call stack. (Alternatively, the contents of the registers may be placed in a system table.)<ref name="sco-ch5-p309"/>
* Read the integer from the data bus. The integer is an offset to the [[interrupt vector table]]. The vector table's instructions will then:
:* Access the device-status table.
:* Extract the process control block.
:* Perform a context switch back to the writing process.

When the writing process has its [[Preemption (computing)#time slice|time slice]] expired, the operating system will:<ref name="sco-ch5-p310">{{cite book
  | last = Tanenbaum
  | first = Andrew S.
  | title = Structured Computer Organization, Third Edition
  | publisher = Prentice Hall
  | year = 1990
  | page = [https://archive.org/details/structuredcomput00tane/page/310 310]
  | isbn = 978-0-13-854662-5
  | url = https://archive.org/details/structuredcomput00tane/page/310
  }}</ref>
* Pop from the call stack the registers other than the status register and program counter.
* Pop from the call stack the status register.
* Pop from the call stack the address of the next instruction, and set it back into the program counter.

With the program counter now reset, the interrupted process will resume its time slice.<ref name="osc-ch2-p31"/>