Editing Parallel ATA (section)

== Specifications ==
The following table shows the names of the versions of the ATA standards and the transfer modes and rates supported by each. Note that the transfer rate for each mode (for example, 66.7&nbsp;MB/s for UDMA4, commonly called "Ultra-DMA 66", defined by ATA-5) gives its maximum theoretical transfer rate on the cable. This is simply two bytes multiplied by the effective clock rate, and presumes that every clock cycle is used to transfer end-user data. In practice, of course, protocol overhead reduces this value.

Congestion on the host bus to which the ATA adapter is attached may also limit the maximum burst transfer rate. For example, the maximum data transfer rate for [[conventional PCI]] bus is 133&nbsp;MB/s, and this is shared among all active devices on the bus.

In addition, no ATA [[hard drive]]s existed in 2005 that were capable of measured sustained transfer rates of above 80&nbsp;MB/s. Furthermore, sustained transfer rate tests do not give realistic throughput expectations for most workloads: They use I/O loads specifically designed to encounter almost no delays from seek time or rotational latency. Hard drive performance under most workloads is limited first and second by those two factors; the transfer rate on the bus is a distant third in importance. Therefore, transfer speed limits above 66&nbsp;MB/s really affect performance only when the hard drive can satisfy all I/O requests by reading from its internal [[disk buffer|cache]]—a very unusual situation, especially considering that such data is usually already buffered by the operating system.

{{As of|2021|7}}, mechanical hard disk drives can transfer data at up to 524&nbsp;MB/s,<ref name="TomMach2">{{cite news |title=Seagate Lists the Mach.2: The World's Fastest HDD |publisher=tomshardware.com |author=Anton Shilov |url=https://www.tomshardware.com/uk/news/seagate-lists-dual-actuator-hdd-exos-2x14 |date=2021-05-21 |access-date=2021-07-20 |archive-url=https://archive.today/20210720224703/https://www.tomshardware.com/uk/news/seagate-lists-dual-actuator-hdd-exos-2x14 |archive-date=2021-07-20 |url-status=live }}</ref> which is far beyond the capabilities of the PATA/133 specification. High-performance [[solid state drives]] can transfer data at up to 7000–7500&nbsp;MB/s.<ref name="TomOptane">{{cite news |title=Intel Optane SSD DC P5800X Review: The Fastest SSD Ever Made |publisher=tomshardware.com |author=Sean Webster |url=https://www.tomshardware.com/reviews/intel-optane-ssd-dc-p5800x-review/3 |date=2021-07-02 |access-date=2021-07-20 |archive-url=https://archive.today/20210720224808/https://www.tomshardware.com/reviews/intel-optane-ssd-dc-p5800x-review/3 |archive-date=2021-07-20 |url-status=live }}</ref>

Only the Ultra DMA modes use [[Cyclic redundancy check|CRC]] to detect errors in data transfer between the controller and drive. This is a 16-bit CRC, and it is used for data blocks only. Transmission of command and status blocks do not use the fast signaling methods that would necessitate CRC. For comparison, in Serial ATA, 32-bit CRC is used for both commands and data.<ref>{{cite web |title=Serial ATA—A Comparison with Ultra ATA Technology |url=http://www.serialata.org/docs/serialata%20-%20a%20comparison%20with%20ultra%20ata%20technology.pdf |archive-url=https://web.archive.org/web/20071203002431/http://www.serialata.org/docs/serialata%2520-%2520a%2520comparison%2520with%2520ultra%2520ata%2520technology.pdf |archive-date=2007-12-03 |url-status=dead}} www.serialata.org</ref>

=== Features introduced with each ATA revision ===
{| class="wikitable" style="text-align:left"
|-
! Standard
! Other names
! New transfer modes
! Maximum disk size<br />(512 byte sector)
! Other significant changes
! ANSI reference
|-
| nowrap|IDE (pre-ATA) || IDE || [[Programmed input/output|PIO]] 0 || 2&nbsp;[[Gibibyte|GiB]] (2.1&nbsp;[[Gigabyte|GB]]) || 22-bit [[logical block addressing]] (LBA) || –
|-
| {{nowrap|ATA-1}} || ATA, IDE || {{nowrap|PIO 0, 1, 2}}<br />{{nowrap|[[WDMA (computer)|Single-word DMA]] 0, 1, 2}}<br />Multi-word DMA 0 || 128&nbsp;[[Gibibyte|GiB]] (137&nbsp;[[Gigabyte|GB]]) || 28-bit logical block addressing (LBA) || [http://www.t13.org/documents/UploadedDocuments/project/d0791r4c-ATA-1.pdf X3.221-1994] {{Webarchive|url=https://web.archive.org/web/20120321035657/http://www.t13.org/Documents/UploadedDocuments/project/d0791r4c-ATA-1.pdf |date=2012-03-21 }}<br />(obsolete since 1999)
|-
| {{nowrap|ATA-2}} || EIDE, {{nowrap|Fast ATA}}, {{nowrap|Fast IDE}}, {{nowrap|Ultra ATA}} || PIO 3, 4<br />[[WDMA (computer)|Multi-word DMA]] 1, 2 || || 44-pin Small Form Factor connector, for ≤2.5″ drives, and [[PCMCIA]] connector. Identify drive command.<ref>{{cite web| url = http://www.mpcclub.com/wiki/images/9/9a/Em8550datasheet.pdf| title = mpcclub.com – Em8550datasheet.pdf| access-date = 2011-05-18| archive-date = 2011-07-25| archive-url = https://web.archive.org/web/20110725070824/http://www.mpcclub.com/wiki/images/9/9a/Em8550datasheet.pdf| url-status = dead}}<!--Page 35--></ref><!--and Page 51 in ATA2 spec Opcode ECh, PIO--> [[Plug and play]] support. || [http://www.t13.org/Documents/UploadedDocuments/project/d0948r4c-ATA-2.pdf X3.279-1996] {{Webarchive|url=https://web.archive.org/web/20110728081254/http://www.t13.org/Documents/UploadedDocuments/project/d0948r4c-ATA-2.pdf |date=2011-07-28 }}<br />(obsolete since 2001)
|-
| {{nowrap|ATA-3}} || EIDE || [[WDMA (computer)|Single-word DMA]] modes dropped<ref>{{cite web| url = http://www.pcguide.com/ref/hdd/if/ide/modesDMA-c.html| title = Direct Memory Access (DMA) Modes and Bus Mastering DMA}}</ref> || || [[Self-Monitoring, Analysis and Reporting Technology|S.M.A.R.T.]], Security || [http://www.t13.org/Documents/UploadedDocuments/project/d2008r7b-ATA-3.pdf X3.298-1997] {{Webarchive|url=https://web.archive.org/web/20140722012229/http://www.t13.org/Documents/UploadedDocuments/project/d2008r7b-ATA-3.pdf |date=2014-07-22 }}<br />(obsolete since 2002)
|-
| {{nowrap|ATA/ATAPI-4}} || ATA-4, {{nowrap|Ultra ATA/33}} || {{nowrap|Ultra DMA 0, 1, 2}},<br />also known as UDMA/33 || || AT Attachment Packet Interface (ATAPI) (support for CD-ROM, tape drives etc.), Optional overlapped and queued command set features, [[Host Protected Area]] (HPA), [[CompactFlash]] Association (CFA) feature set for solid state drives || [http://www.t13.org/documents/UploadedDocuments/project/d1153r18-ATA-ATAPI-4.pdf NCITS 317-1998] {{Webarchive|url=https://web.archive.org/web/20140722012712/http://www.t13.org/Documents/UploadedDocuments/project/d1153r18-ATA-ATAPI-4.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.t13.org/Documents/UploadedDocuments/project/d1153r18-ATA-ATAPI-4.pdf |archive-date=2022-10-09 |url-status=live |date=2014-07-22 }} {{anchor|NCITS_317-1998}}
|-
| {{nowrap|ATA/ATAPI-5}} || ATA-5, {{nowrap|Ultra ATA/66}} || Ultra DMA 3, 4,<br />also known as UDMA/66 || || 80-wire cables; [[CompactFlash]] connector || [http://www.t13.org/documents/UploadedDocuments/project/d1321r3-ATA-ATAPI-5.pdf NCITS 340-2000] {{Webarchive|url=https://web.archive.org/web/20140722012756/http://www.t13.org/Documents/UploadedDocuments/project/d1321r3-ATA-ATAPI-5.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.t13.org/Documents/UploadedDocuments/project/d1321r3-ATA-ATAPI-5.pdf |archive-date=2022-10-09 |url-status=live |date=2014-07-22 }}
|-
| {{nowrap|ATA/ATAPI-6}} || ATA-6, {{nowrap|Ultra ATA/100}} || UDMA 5,<br />also known as UDMA/100|| 128&nbsp;[[Pebibyte|PiB]] (144&nbsp;[[Petabyte|PB]]) || 48-bit LBA, [[Device Configuration Overlay]] (DCO),<br />[[Automatic Acoustic Management]] (AAM)<br /> [[Cylinder-head-sector|CHS]] method of addressing data obsolete || [http://www.t13.org/Documents/UploadedDocuments/project/d1410r3b-ATA-ATAPI-6.pdf NCITS 361-2002] {{Webarchive|url=https://web.archive.org/web/20110915154404/http://www.t13.org/Documents/UploadedDocuments/project/d1410r3b-ATA-ATAPI-6.pdf |date=2011-09-15 }}
|-
| {{nowrap|ATA/ATAPI-7}} || ATA-7, {{nowrap|Ultra ATA/133}} || UDMA 6,<br />also known as UDMA/133<br />SATA/150 || || [[Serial ATA|SATA]] 1.0, Streaming feature set, long logical/physical sector feature set for non-packet devices || {{nowrap|[http://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v1r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_1.pdf INCITS 397-2005 (vol 1)] {{Webarchive |url=https://web.archive.org/web/20200806045654/https://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v1r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_1.pdf |date=2020-08-06}}}} {{nowrap|[http://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v2r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_2.pdf INCITS 397-2005 (vol 2)] {{Webarchive |url=https://web.archive.org/web/20200616160900/https://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v2r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_2.pdf |date=2020-06-16}}}} {{nowrap|[http://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v3r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_3.pdf INCITS 397-2005 (vol 3)] {{Webarchive |url=https://web.archive.org/web/20200615183913/https://www.t13.org/Documents/UploadedDocuments/docs2007/D1532v3r4b-AT_Attachment_with_Packet_Interface_-_7_Volume_3.pdf |date=2020-06-15}}}}
|-
| {{nowrap|ATA/ATAPI-8}} || ATA-8 || SATA/300<br />SATA/600 || || [[Hybrid drive]] featuring non-volatile cache to speed up critical OS files || [http://www.t13.org/documents/uploadeddocuments/docs2008/d1699r6a-ata8-acs.pdf INCITS 452-2008] {{Webarchive|url=https://web.archive.org/web/20141010045105/http://www.t13.org/documents/UploadedDocuments/docs2008/D1699r6a-ATA8-ACS.pdf |date=2014-10-10 }}
|-
| {{nowrap|ACS-2}} || — ||&nbsp;— || ||Data Set Management, Extended Power Conditions, CFast, additional stats., etc. || [http://www.t13.org/documents/UploadedDocuments/docs2011/d2015r7-ATAATAPI_Command_Set_-_2_ACS-2.pdf INCITS 482-2012] {{Webarchive|url=https://web.archive.org/web/20160701095638/http://www.t13.org/documents/UploadedDocuments/docs2011/d2015r7-ATAATAPI_Command_Set_-_2_ACS-2.pdf |date=2016-07-01 }}
|-
| {{nowrap|ACS-3}} || — ||&nbsp;— || || ||
|-
| {{nowrap|ACS-4}} || — ||&nbsp;— || || Zoned ATA Command ||
|}

=== Speed of defined transfer modes ===
{| class="wikitable sortable" style="text-align:center"
|+ Transfer modes
! Mode || # ||Maximum transfer<br /> rate(MB/s) || Cycle time
|-
| rowspan=5 | [[Programmed input/output|PIO]]
| 0 || 3.3 || 600 ns
|-
| 1 || 5.2 || 383 ns
|-
| 2 || 8.3 || 240 ns
|-
| 3 || 11.1 || 180 ns
|-
| 4 || 16.7 || 120 ns
|- style="background:#f5fffa"
| rowspan=3 | [[WDMA (computer)|Single-word DMA]]
| 0 || 2.1 || 960 ns
|- style="background:#f5fffa"
| 1 || 4.2 || 480 ns
|- style="background:#f5fffa"
| 2 || 8.3 || 240 ns
|-
| rowspan=5 | [[WDMA (computer)|Multi-word DMA]]
| 0 || 4.2 || 480 ns
|-
| 1 || 13.3 || 150 ns
|-
| 2 || 16.7 || 120 ns
|-
| 3<ref name=CompactFlash>[[CompactFlash]] 2.1</ref> || 20 || 100 ns
|-
| 4<ref name=CompactFlash /> || 25 || 80 ns
|- style="background:#f5fffa"
| rowspan=8 | [[UDMA|Ultra DMA]]
| 0 || 16.7 || 240 ns ÷ 2
|- style="background:#f5fffa"
| 1 || 25.0 || 160 ns ÷ 2
|- style="background:#f5fffa"
| 2 (Ultra ATA/33) || 33.3 || 120 ns ÷ 2
|- style="background:#f5fffa"
| 3 || 44.4 || 90 ns ÷ 2
|- style="background:#f5fffa"
| 4 (Ultra ATA/66)|| 66.7 || 60 ns ÷ 2
|- style="background:#f5fffa"
| 5 (Ultra ATA/100)|| 100 || 40 ns ÷ 2
|- style="background:#f5fffa"
| 6 (Ultra ATA/133)|| 133 || 30 ns ÷ 2
|- style="background:#f5fffa"
| 7 (Ultra ATA/167)<ref>{{cite web |url = http://compactflash.org/2010/cf-6-0-introduces-industry-leading-performance-and-feature-enhancements/ |title = CompactFlash 6.0 |archive-url=https://web.archive.org/web/20101121233926/http://compactflash.org/2010/cf-6-0-introduces-industry-leading-performance-and-feature-enhancements/ |archive-date=21 November 2010 |url-status=dead}}</ref>|| 167 || 24 ns ÷ 2
|}