Editing Phase-locked loop (section)

==Elements==

===Phase detector===
{{Main|phase detector}}
A phase detector (PD) generates a voltage, which represents the phase difference between two signals. In a PLL, the two inputs of the phase detector are the reference input and the feedback from the VCO. The PD output voltage is used to control the VCO such that the phase difference between the two inputs is held constant, making it a negative feedback system.
<ref>{{Cite book|last1=Basab Bijoy Purkayastha|title=A Digital Phase Locked Loop based Signal and Symbol Recovery System for Wireless Channel|last2=Kandarpa Kumar Sarma|publisher=Springer (India) Pvt. Ltd. (Part of Springer Scinece+Business Media)|year=2015|isbn=978-81-322-2040-4|location=India|pages=94}}</ref>

Different types of phase detectors have different performance characteristics.

For instance, the [[frequency mixer]] produces harmonics that adds complexity in applications where spectral purity of the VCO signal is important. The resulting unwanted (spurious) sidebands, also called "[[reference spurs]]" can dominate the filter requirements and reduce the capture range well below or increase the lock time beyond the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output. Also, when in lock, the steady-state phase difference at the inputs using this type of phase detector is near 90 degrees.{{citation needed|date=August 2018}}

In PLL applications it is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition.

An [[XOR gate]] is often used for digital PLLs as an effective yet simple phase detector. It can also be used in an analog sense with only slight modification to the circuitry.

===Filter===
The block commonly called the PLL loop filter (usually a low-pass filter) generally has two distinct functions.

The primary function is to determine loop dynamics, also called [[Nyquist stability criterion|stability]]. This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range, lock range or capture range), how fast the loop achieves lock (lock time, lock-up time or [[settling time]]) and [[Damping factor|damping]] behavior. Depending on the application, this may require one or more of the following: a simple proportion (gain or attenuation), an [[integral]] (low-pass filter) and/or [[derivative]] ([[high-pass filter]]). Loop parameters commonly examined for this are the loop's [[gain margin]] and [[phase margin]]. Common concepts in [[control theory]] including the [[PID controller]] are used to design this function.

The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called "reference spurs".

The design of this block can be dominated by either of these considerations, or can be a complex process juggling the interactions of the two. The typical trade-off of increasing the bandwidth is degraded stability. Conversely, the tradeoff of extra damping for better stability is reduced speed and increased settling time. Often the phase-noise is also affected.<ref name=":0" />

===Oscillator===
{{Main|Electronic oscillator}}
All phase-locked loops employ an oscillator element with variable frequency capability. This can be an analog VCO either driven by analog circuitry in the case of an APLL or driven digitally through the use of a [[digital-to-analog converter]] as is the case for some DPLL designs. Pure digital oscillators such as a numerically controlled oscillator are used in ADPLLs.{{citation needed|date=October 2017}}

===Feedback path and optional divider===
{{More citations needed|section|date=June 2022}}[[File:Divide 4.svg|thumb|An example digital divider (by 4) for use in the feedback path of a multiplying PLL]]
PLLs may include a divider between the oscillator and the feedback input to the phase detector to produce a [[frequency synthesizer]]. A programmable divider is particularly useful in radio transmitter applications and for computer clocking, since a large number of frequencies can be produced from a single stable, accurate, [[crystal oscillator|quartz crystal–controlled reference oscillator]] (which were expensive before commercial-scale [[hydrothermal synthesis]] provided cheap synthetic quartz).

Some PLLs also include a divider between the reference clock and the reference input to the phase detector. If the divider in the feedback path divides by <math>N</math> and the reference input divider divides by <math>M</math>, it allows the PLL to multiply the reference frequency by <math>N/M</math>. It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may be constrained by other issues, and then the reference divider is useful.

Frequency multiplication can also be attained by locking the VCO output to the ''N''th harmonic of the reference signal. Instead of a simple phase detector, the design uses a harmonic mixer (sampling mixer). The harmonic mixer turns the reference signal into an impulse train that is rich in harmonics.{{Efn|Typically, the reference sinewave drives a [[step recovery diode]] circuit to make this impulse train. The resulting impulse train drives a sample gate.}} The VCO output is coarse tuned to be close to one of those harmonics. Consequently, the desired harmonic mixer output (representing the difference between the ''N'' harmonic and the VCO output) falls within the loop filter passband.<!-- HP had a harmonic mixer and synchronizer that turned its microwave sweep generators into PLLs. -->

It should also be noted that the feedback is not limited to a frequency divider. This element can be other elements such as a frequency multiplier, or a mixer. The multiplier will make the VCO output a sub-multiple (rather than a multiple) of the reference frequency. A mixer can translate the VCO frequency by a fixed offset. It may also be a combination of these. For example, a divider following a mixer allows the divider to operate at a much lower frequency than the VCO without a loss in loop gain.