Editing Zilog Z80 (section)

=== Instruction execution ===
Each instruction is executed in steps that are usually termed [[machine cycle]]s (M-cycles), each of which can take between three and six clock periods (T-states).<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |page=7 |chapter=Timing |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |archive-date=December 26, 2023 |url-status=live}}</ref> Each M-cycle corresponds roughly to one memory access or internal operation. Multiple instructions actually end during the M1 of the ''next'' instruction which is known as a ''fetch/execute overlap''.

{| class="wikitable"
|+ Examples of typical instructions (R=read, W=write)
! Total
M-cycles
! T-states
! instruction
! M1
! M2
! M3
! M4
! M5
! M6
|-
| 1{{sfnp|Ciarcia|1981|p=65}}
| 4<ref name="Zilog 2005" />
| <syntaxhighlight lang="nasm" inline>INC B</syntaxhighlight>
| opcode
| ||
| || ||
|-
| 2<ref>{{Cite book |last=Zaks |first=Rodnay |url=https://archive.org/details/Programming_The_Z80_Third_Edition_Rodnay_Zaks/ |title=Programming the Z80 |date=1989 |publisher=Sybex |isbn=978-0-89588-069-7 |page=200 |quote=ADD A, n Add accumulator with immediate data n. MEMORY Timing: 2 M cycles; 7 T states. |issue=69}}</ref>
| 7
| <syntaxhighlight lang="nasm" inline>ADD A,n</syntaxhighlight>
| opcode
| n
| ||
| ||
|-
| 3{{sfnp|Ciarcia|1981|p=63}}
| 11
| <syntaxhighlight lang="nasm" inline>ADD HL,DE</syntaxhighlight>
| opcode
| internal
| internal
| || ||
|-
| 4{{sfnp|Ciarcia|1981|p=77}}
| 15
| <syntaxhighlight lang="nasm" inline>SET b,(HL)</syntaxhighlight>
| prefix
| opcode
| R(HL), set
| W(HL)
| ||
|-
| 5{{sfnp|Ciarcia|1981|p=36}}
| 19
| <syntaxhighlight lang="nasm" inline>LD (IX+d),n</syntaxhighlight>
| prefix
| opcode
| d
| n,add
| W(IX+d) ||
|-
| 6{{sfnp|Ciarcia|1981|p=58}}
| 23
| <syntaxhighlight lang="nasm" inline>INC (IY+d)</syntaxhighlight>
| prefix
| opcode
| d
| add
|R(IY+d),inc
| W(IY+d)
|}

The Z80 machine cycles are sequenced by an internal [[state machine]] which builds each M-cycle out of 3, 4, 5 or 6 T-states depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on [[memory access time]]s, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.{{citation needed|date=December 2012}}

One central example of this is that, for [[opcode fetch]], the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the [[Motorola 6800|6800]], [[MOS Technology 6502|6502]], or similar, where this period would typically last typically 30-40% of a clock cycle.{{citation needed|date=November 2012}} With memory chip affordability (i.e. access times around 450-250&nbsp;ns in the 1980s{{citation needed|date=November 2012}}) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.

Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding [[Static random access memory|SRAM]]; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.

The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus.<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |page=3 |chapter=Special-Purpose Registers |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1012169 |archive-date=December 26, 2023 |url-status=live}}</ref>