Editing Communicating sequential processes (section)

=== ARC ===

The ''Adelaide Refinement Checker'' (''ARC'')<ref>{{cite conference |first1=Atanas N. |last1=Parashkevov |first2=Jay |last2=Yantchev |title=ARC – a tool for efficient refinement and equivalence checking for CSP |book-title=IEEE Int. Conf. on Algorithms and Architectures for Parallel Processing ICA3PP '96 |pages=68–75 |date=1996 |citeseerx=10.1.1.45.3212}}</ref> is a CSP refinement checker developed by the Formal Modelling and Verification Group at [[The University of Adelaide]]. ARC differs from FDR2 in that it internally represents CSP processes as [[Binary decision diagram|Ordered Binary Decision Diagrams]] (OBDDs), which alleviates the state explosion problem of explicit LTS representations without requiring the use of state-space compression algorithms such as those used in FDR2.