Editing Itanium (section)

==== Others ====
In May 2003, IBM launched the XA-64 chipset for Itanium 2. It used many of the same technologies as the first two generations of XA-32 chipsets for [[Xeon]], but by the time of the third gen XA-32 IBM had decided to discontinue its Itanium products. XA-64 supported 56 GB of [[DDR SDRAM]] in 28 slots at 6.4 GB/s, though due to bottlenecks only 3.2 GB/s could go to the CPU and other 2 GB/s to devices for a 5.2 GB/s total. The CPU's memory bottleneck was mitigated by an off-chip 64 MB [[DRAM]] L4 cache, which also worked as a [[Bus snooping#Snoop filter|snoop filter]] in multi-chipset systems. The combined bandwidth of the four [[PCI-X]] buses and other I/O is bottlenecked to 2 GB/s per chipset. Two or four chipsets can be connected to make an 8 or 16 socket system.<ref>{{cite web |title=IBM Eserver xSeries 455 Planning and Installation Guide |url=https://lenovopress.com/sg247056.pdf |publisher=IBM/Lenovo |access-date=6 April 2022}}</ref>

[[Silicon Graphics|SGI]]'s [[Altix]] supercomputers and servers used the SHUB (Super-Hub) chipset, which supports two Itanium 2 sockets. The initial version used [[DDR SDRAM|DDR memory]] through four buses for up to 12.8 GB/s bandwidth, and up to 32 GB of capacity across 16 slots. A 2.4 GB/s [[XIO]] channel connected to a module with up to six 64-bit 133&nbsp;MHz [[PCI-X]] buses. SHUBs can be interconnected by the dual 6.4 GB/s [[NUMAlink]]4 link planes to create a 512-socket cache-coherent single-image system. A cache for the in-memory [[Directory-based cache coherence|coherence directory]] saves memory bandwidth and reduces latency. The latency to the local memory is 132 ns, and each crossing of a NUMAlink4 router adds 50 ns. I/O modules with four 133&nbsp;MHz PCI-X buses can connect directly to the NUMAlink4 network.<ref>{{cite web |last1=Woodacre |first1=Michael |last2=Robb |first2=Derek |last3=Roe |first3=Dean |last4=Feind |first4=Karl |title=The SGI® Altix 3000 Global Shared-Memory Architecture |url=http://www.sgi.com/pdfs/3474.pdf |website=sgi.com |archive-url=https://web.archive.org/web/20060314142114/http://www.sgi.com/pdfs/3474.pdf |archive-date=2006-03-14 |url-status=dead}}</ref><ref>{{cite web |last1=Vogelsang |first1=Reiner |title=SGI® Altix™ Hardware Architecture |url=https://moodle.risc.jku.at/file.php/50/altix_hardware.pdf |access-date=25 April 2022 }}</ref><ref>{{cite web |title=SGI® Altix™ 350 System User's Guide |url=http://techpubs.sgi.com/library/manuals/4000/007-4660-002/pdf/007-4660-002.pdf |archive-url=https://web.archive.org/web/20160121032040/http://techpubs.sgi.com/library/manuals/4000/007-4660-002/pdf/007-4660-002.pdf |archive-date=2016-01-21 |url-status=dead}}</ref><ref>{{cite web |title=SGI® Altix® 3000 Servers and Superclusters |url=http://www.sgi.com/pdfs/3392.pdf |archive-url=https://web.archive.org/web/20060314165928/http://www.sgi.com/pdfs/3392.pdf |archive-date=2006-03-14 |url-status=dead}}</ref> SGI's second-generation SHUB 2.0 chipset supported up to 48 GB of [[DDR2 SDRAM|DDR2]] memory, 667 MT/s FSB, and could connect to I/O modules providing [[PCI Express]].<ref>{{cite web |title=SGI® Altix® 4700 Servers and Supercomputers |url=http://www.sgi.com/pdfs/3867.pdf |archive-url=https://web.archive.org/web/20051124042540/http://www.sgi.com/pdfs/3867.pdf |archive-date=2005-11-24 |url-status=dead}}</ref><ref>{{cite web |last1=Vogelsang |first1=Reiner |title=SGI® Altix™ Hardware Architecture |url=https://wwwuser.gwdg.de/~parallel/parallelrechner/altix_documentation/Altix_Hardware_revised_4.pdf |access-date=4 July 2023}}</ref> It supports only four local threads, so when having two dual-core CPUs per chipset, [[Hyper-Threading]] must be disabled.<ref>{{cite web |title=SGI® L1 and L2 Controller Software User's Guide |url=http://techpubs.sgi.com/library/manuals/3000/007-3938-006/pdf/007-3938-006.pdf |archive-url=https://web.archive.org/web/20151203105150/http://techpubs.sgi.com/library/manuals/3000/007-3938-006/pdf/007-3938-006.pdf |archive-date=2015-12-03 |url-status=dead}}</ref>