Editing List of AMD Athlon processors (section)

===="Carrizo" (2016)====
* [[28 nm process|28&nbsp;nm fabrication]] by [[GlobalFoundries]]
* Socket [[Socket FM2+|FM2+]], [[Socket AM4|AM4]], support for [[PCI Express#3.0|PCIe 3.0]]
* Two or four CPU cores based on the [[Excavator (microarchitecture)|Excavator]] microarchitecture
* Die Size: {{val|250.04|u=mm2}}, 3.1 Billion transistors<ref>{{cite web |author1=Hassan Mujtaba |title=AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 – 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die |url=https://wccftech.com/amd-carrizo-apu-architecture-hot-chips/ |website=Wccftech |access-date=20 March 2020 |date=26 August 2015}}</ref>
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[SSE4a]], [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[Advanced Vector Extensions 2|AVX2]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], [[Turbo Core]]
* Dual-channel DDR3 or [[DDR4 SDRAM|DDR4]] memory controller

{| class="wikitable" style="text-align:center"
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | [[Stepping level|Stepping]]
! rowspan="3" | Socket
! colspan="5" | CPU
! rowspan="3" | Memory<br>support
! rowspan="3" | TDP
! rowspan="3" | Part number
|-
! rowspan="2" |[Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" |[[Clock rate|Clock (GHz)]]
! colspan="2" |[[Cache memory|Cache]]
|-
! Base
! Turbo
! [[L1 cache|L1]]
! [[L2 cache|L2]]
|-
! [https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/835.html Athlon X4 835]
| ?
| rowspan="2" | CZ-A1
| rowspan="2" | FM2+
| rowspan="2" | [2] 4
| 3.1
| ?
| rowspan="2" | 96 KB<br><small>inst.<br>per module</small><br>32 KB<br><small>data<br>per core</small>
| rowspan="2" | 1 MB<br><small>per module</small>
| rowspan="2" | DDR3-2133<br><small>dual-channel</small>
| rowspan="2" | 65&nbsp;W
| AD835XACI43KA
|-
! [https://www.amd.com/en/products/cpu/845-near-silent-thermal-solution Athlon X4 845]
|Feb 2, 2016
|3.5
|3.8
|AD845XYBJCSBX{{efn|name="box"|Boxed part with cooler if available.}}<br>AD845XACKASBX{{efn|name="box"}} <br>AD845XACI43KA
|}
{{notelist}}