Editing MOS Technology 6502 (section)

==Variations and derivatives {{anchor|variants|Variants}}==
The 6502 was the most prolific variant of the 65xx series family from [[MOS Technology]].

The 6501 and 6502 have 40-pin [[dual inline package|DIP]] packages; the 6503, 6504, 6505, and 6507 are 28-pin DIP versions, for reduced chip and circuit board cost. In all of the 28-pin versions, the pin count is reduced by leaving off some of the high-order address pins and various combinations of function pins, making those functions unavailable.

{| class="wikitable" style="text-align: center; width: 500px;"
|+ Pinout differences
|-
! Pin || 6800 !! 6501 !! 6502
|-
| 2 || Halt || Ready || Ready
|-
| 3 || ∅1 (in) ||∅1 (in) || ∅1 (out)
|-
| 5 || Valid memory address || Valid memory address || N.C.
|-
| 7 || Bus available || Bus available || SYNC
|-
| 36 || Data bus enable || Data bus enable || N.C.
|-
| 37 || ∅2 (in) || ∅2 (in) || ∅0 (in)
|-
| 38 || N.C. || N.C. || Set overflow flag
|-
| 39 || Three-state control || N.C. || ∅2 (out)
|}

Typically, the 12 pins omitted to reduce the pin count from 40 to 28 are the three [[not connected]] (NC) pins, one of the two Vss pins, one of the clock pins, the SYNC pin, the set overflow (SO) pin, either the maskable interrupt or the non-maskable interrupt (NMI), and the four most-significant address lines (A12&ndash;A15).  The omission of four address pins reduces the external addressability to 4&nbsp;KB (from the 64&nbsp;KB of the 6502), though the internal PC register and all effective address calculations remain [[16-bit computing|16-bit]].

The [[MOS Technology 6507|6507]] omits both interrupt pins in order to include address line A12, providing 8 KB of external addressability but no interrupt capability.  The 6507 was used in the popular [[Atari 2600]] video game console, the design of which divides the 8 KB memory space in half, allocating the lower half to the console's internal RAM and peripherals, and the upper half to the Game Cartridge, so Atari 2600 cartridges have a 4 KB address limit (and the same capacity limit unless the cartridge contains [[bank switching]] circuitry).

One popular 6502-based computer, the [[Commodore 64]], used a modified 6502 CPU, the [[MOS Technology 6510|6510]]. Unlike the 6503&ndash;6505 and 6507, the 6510 is a 40-pin chip that adds internal hardware: a 6-bit parallel I/O port mapped to addresses 0000 and 0001. The [[MOS Technology 6508|6508]] is another chip that, like the 6510, adds internal hardware: 256 bytes of [[Static random-access memory|SRAM]] and an 8-bit I/O port similar to those featured by the 6510. Though these chips do not have reduced pin counts compared to the 6502, they need new pins for the added parallel I/O port.  In this case, no address lines are among the removed pins.

{| class="wikitable sortable"
|+ Variations
|-
! Company
! Model
! Description
|-
| 
| data-sort-value="6502"|6502
| A 1&nbsp;MHz chip used in ''[[KIM-1]]'' and other single board computers in the mid-1970s.
|-
| 
| data-sort-value="6502A"|6502A
| A 1.5&nbsp;MHz chip used in ''[[Asteroids Deluxe]]'' and at 2&nbsp;MHz in the [[BBC Micro]]
|-
| 
| data-sort-value="6502B"|6502B 
| Version of the 6502 capable of running at a maximum speed of 3&nbsp;MHz instead of 2&nbsp;MHz. The B was used in both the [[Apple III]] and early [[Atari 8-bit computers]], each running at ~1.8&nbsp;MHz.{{efn|name=ntsc|reference=More precisely these systems internally divide an [[NTSC]] [[colorburst crystal]] yielding {{frac|315|176}}&nbsp;Mhz = 1.78977{{overbar|27}}&nbsp;MHz}}
|-
| 
| data-sort-value="6502C"|6502C
| The “official” 6502C was a version of the original 6502 able to run at up to 4&nbsp;MHz.

Not to be confused with SALLY, a custom 6502 designed for Atari (and sometimes referred to by them as "6502C"<ref name='am_sally'/>) nor with the similarly named [[65C02]].
|-
| 
| data-sort-value="SALLY"|SALLY, C014806, "6502C"
| {{anchor|sally}}Custom 6502 variant designed for Atari, used in later [[Atari 8-bit computers]] and [[Atari 5200]] and [[Atari 7800]] consoles.

Has a HALT signal on pin 35 and the R/W signal on pin 36 (these pins are not connected (N/C) on a standard 6502). Pulling HALT low latches the clock, pausing the processor. This was used to allow the video circuitry direct memory access (DMA).<ref>{{Cite book|title=ATARI 1200 XL HOME COMPUTER FIELD SERVICE MANUAL|publisher=ATARI|date=February 1983|chapter=6502 (modified) CPU Microprocessor}}</ref>

Although sometimes referred to as "6502C" in Atari documentation, this is not the same as the ''official'' 6502C and the chip itself is never marked as such.<ref name='am_sally'>{{cite web|url=http://www.atarimania.com/faq-atari-400-800-xl-xe-what-are-sally-antic-ctia-gtia-fgtia-pokey-and-freddie_14.html|title=FAQ 400 800 XL XE: What are SALLY, ANTIC, CTIA/GTIA/FGTIA, POKEY, and FREDDIE?|quote=named SALLY by Atari engineers, but [support documents call it] "6502 (Modified)", "6502 Modified", "Custom 6502", or "6502C". [..] SALLY 6502 chips are never marked "6502C" but, other than the UMC UM6502I, always [marked] C014806. [..] [Other] chips marked "6502C" [..] are NOT the Atari "6502C" but [standard 6502] certified for 4MHz|archiveurl=https://web.archive.org/web/20200719024918/http://www.atarimania.com/faq-atari-400-800-xl-xe-what-are-sally-antic-ctia-gtia-fgtia-pokey-and-freddie_14.html|archivedate=19 July 2020}}</ref>

|-
|-
| MOS
| data-sort-value="6503"|[[MOS Technology 6503|6503]]
| Reduced memory addressing capability (4 KB) and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA">1982 MOS Technology Data Catalog (PDF obtained from bitsavers.org)</ref>
|-
| MOS
| data-sort-value="6504"|[[MOS Technology 6504|6504]]
| Reduced memory addressing capability (8 KB), no NMI, and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6505"|[[MOS Technology 6505|6505]]
| Reduced memory addressing capability (4 KB) and no NMI, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6506"|[[MOS Technology 6505|6506]]
| Reduced memory addressing capability (4 KB), no NMI, and no RDY input, but all 3 clock pins of the 6502 (i.e. a 2-phase output clock), in a 28-pin DIP package (with the SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/>
|-
| MOS
| data-sort-value="6507"|[[MOS Technology 6507|6507]]
| Reduced memory addressing capability (8 KB) and no interrupts, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).<ref name="ReferenceA"/> This chip was used in the [[Atari 2600]] video game system.
|-
| MOS
| data-sort-value="6508"|[[MOS Technology 6508|6508]]
| Has a built-in 8-bit input/output port and 256 bytes of internal static RAM.
|-
| MOS
| data-sort-value="6509"|[[MOS Technology 6509|6509]]
| Can address up to 1&nbsp;MB of RAM as 16 banks of 64&nbsp;KB and was used in the Commodore [[CBM-II]] series.
|-
| MOS
| data-sort-value="6510"|[[MOS Technology 6510|6510]]
| Has a built-in 6-bit programmable input/output port and was used in the [[Commodore 64]]. The 8500 is effectively an HMOS version of the 6510, and replaced it in later versions of the C64.
|-
| MOS
| data-sort-value="6512"|[[MOS Technology 6512|6512]]<br/>[[MOS Technology 6513|6513]]<br/>[[MOS Technology 6514|6514]]<br/>[[MOS Technology 6515|6515]]
| The MOS Technology 6512, 6513, 6514, and 6515 each rely on an external clock, instead of using an internal clock generator like the 650x (e.g. 6502). This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.

The 6512 is a 6502 with a 2-phase clock input for an external clock oscillator, instead of an on-board clock oscillator.<ref name="ReferenceA"/> The 6513, 6514 and 6515 are similarly equivalent to (respectively) a 6503, 6504 and 6505 with the same 2-phase clock input.<ref name="ReferenceA"/>

The 6512 was used in the [[BBC Micro|BBC Micro B+64]].
|-
| Ricoh
| data-sort-value="RP2A03"|[[Ricoh 2A03|RP2A03]]<br/>RP2A07
| Unlicensed 6502 variants running at ~1.8&nbsp;MHz{{efn|name=ntsc}} including an audio processing unit but lacking the BCD mode, used in the [[Nintendo Entertainment System]].
|-
| MOS
| data-sort-value="6591"|[[MOS Technology 6591|6591]]<br/>6592
| [[System on a chip]] designs that utilize a complete [[Atari 2600]] in a 48-pin DIP package.<ref>{{Cite web |url=https://atariage.com/forums/topic/241219-a2600-clone-6591-chip-pinout/?tab=comments#comment-3291842 |title=AtariAge: A2600 clone, 6591 chip pinout |date=3 August 2015 |access-date=2019-07-22 |archive-date=2020-08-05 |archive-url=https://web.archive.org/web/20200805060921/https://atariage.com/forums/topic/241219-a2600-clone-6591-chip-pinout/?tab=comments#comment-3291842 |url-status=live}}</ref><ref>{{Cite web |url=https://hackaday.com/2012/04/07/the-teensiest-atari-2600-ever/ |title=Hackaday: The teensiest Atari 2600 ever |date=7 April 2012 |access-date=2019-07-22 |archive-date=2019-07-22 |archive-url=https://web.archive.org/web/20190722203421/https://hackaday.com/2012/04/07/the-teensiest-atari-2600-ever/ |url-status=live}}</ref>
|-
| WDC
| data-sort-value="65C02"|[[65C02]]
| [[CMOS]] version of the NMOS 6502 that was designed by [[Bill Mensch]] of the [[Western Design Center]] (WDC), featuring reduced power consumption, support for much higher clock speeds, new instructions, new addressing modes for some existing instructions, and correction of NMOS errata, such as the <code>JMP ($xxFF)</code> bug.
|-
| data-sort-value="MOS Technology"|CSG, MOS
| data-sort-value="65CE02"|[[CSG 65CE02|65CE02]]
| CMOS variant developed by the [[Commodore Semiconductor Group]] (CSG), formerly MOS Technology.  The 65CE02 provides a further enhanced instruction set from the 65C02, featuring a third indexing register (Z), base page register, 16-bit stack and faster program execution with the minimal instruction timing reduced from 2 to 1 clock cycles.
|-
| Rockwell
| data-sort-value="R6511Q"|R6511Q<br/><br/>R6500/11, R6500/12, R6500/15 "''One-Chip Microcomputers''"
| Enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip 192-byte zero-page RAM, [[UART]], etc.<ref>{{cite web
|title=Rockwell R6511Q
|url=http://www.cpu-world.com/CPUs/6500/Rockwell-R6511Q.html
|access-date=30 Apr 2020
|archive-date=15 September 2020
|archive-url=https://web.archive.org/web/20200915151513/http://www.cpu-world.com/CPUs/6500/Rockwell-R6511Q.html
|url-status=live
}}</ref><ref>{{cite web
|title=Rockwell R6500/11, R6500/12 and R6500/15 One-Chip Microcomputers
|url=https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|date=7 Jun 1987
|access-date=30 Apr 2020
|archive-date=4 August 2020
|archive-url=https://web.archive.org/web/20200804041549/https://datasheetspdf.com/pdf-file/1338410/Rockwell/R6500-11/1
|url-status=live
}}</ref>
|-
| Rockwell
| R65F11<br/>R65F12
| The Rockwell R65F11 (introduced in 1983) and the later R65F12 are enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip zero-page RAM, on-chip [[Forth (programming language)|Forth]] kernel ROM, a UART, etc.<ref>Randy M. Dumse.
"The R65F11 and F68K Single-Chip Forth Computers".
[http://www.forth.org/bournemouth/jfar/vol2/no1/article1.pdf]{{dead link|date=May 2017|bot=InternetArchiveBot|fix-attempted=yes}}
[http://soton.mpeforth.com/flag/jfar/vol2/no1/article1.pdf] {{Webarchive|url=https://web.archive.org/web/20141202144044/http://soton.mpeforth.com/flag/jfar/vol2/no1/article1.pdf|date=2014-12-02}}
1984.</ref><ref>
Ed Schmauch.
[http://www.forth.org/bournemouth/jfar/vol4/no2/article48.pdf "A Computerized Corrosion Monitoring System"]{{dead link|date=May 2017 |bot=InternetArchiveBot |fix-attempted=yes}}.
1986.
</ref><ref>Lawrence P. Forsley.
[https://books.google.com/books?id=Yx8YAQAAMAAJ "Embedded systems: 1990 Rochester Forth Conference: June 12 – 16th, 1990 University of Rochester"] {{Webarchive|url=https://web.archive.org/web/20150325214054/http://books.google.com/books?id=Yx8YAQAAMAAJ |date=2015-03-25}}.
p. 51.</ref><ref>Rockwell.
[http://www.smallestplcoftheworld.org/RSC-FORTH_User's_Manual.pdf "RSC-Forth User's Manual"] {{Webarchive|url=https://web.archive.org/web/20131207015149/http://smallestplcoftheworld.org/RSC-FORTH_User%27s_Manual.pdf |date=2013-12-07}}.
1983.</ref><ref>{{cite web
|title=Rockwell R65F11 R65F12 Forth Based Microcomputers
|url=http://archive.6502.org/datasheets/rockwell_r65f11_r65f12_forth_microcomputers.pdf
|date=June 1987
|access-date=28 Apr 2020
|archive-date=4 August 2020
|archive-url=https://web.archive.org/web/20200804035007/http://archive.6502.org/datasheets/rockwell_r65f11_r65f12_forth_microcomputers.pdf
|url-status=live
}}</ref>
|-
| GTE
| data-sort-value="G65SC12"|G65SC12
| Drop in 6502 CMOS variant without individual bit manipulation operations (RMB, SMB, BBR and BBS).<ref>{{cite book |first=Rodnay |last=Zaks |title=Programming the 6502 |page=348}}</ref>  This was used in the [[BBC Master]].
|-
| GTE
| data-sort-value="G65SC102"|G65SC102 
| Software compatible with the 6502, but has a slightly different pinout and oscillator circuit. The [[BBC Master]] Turbo included the 4&nbsp;MHz version of this CPU on a coprocessor card, which could also be bought separately and added to the Master 128.
|-
| Rockwell
| R65C00<br/>R65C21<br/>R65C29
| The R65C00, R65C21, and R65C29 have two enhanced CMOS 6502s in a single chip, and the R65C00 and R65C21 additionally contained 2&nbsp;KB of mask-programmable ROM.<ref>{{cite web |url=http://www.datasheetarchive.com/dl/Scans-055/DSAIH000103824.pdf |title=Arquivo.pt |access-date=2014-10-26 |url-status=dead |archive-url=http://arquivo.pt/wayback/20160515111805/http%3A//www.datasheetarchive.com/dl/Scans%2D055/DSAIH000103824.pdf |archive-date=2016-05-15}}</ref><ref>{{cite web|url=https://archive.org/details/bitsavers_rockwelldaDataBook_80778847|title=rockwell :: dataBooks :: 1985 Rockwell Data Book|via=Internet Archive}}</ref>
|-
| 
| data-sort-value="CM630"|{{anchor|CM630}}CM630
| A 1&nbsp;MHz [[Eastern Bloc]] clone of the 6502 and was used in the [[Pravetz computers|Pravetz]] 8A and 8C, Bulgarian clones of the [[Apple II]].<ref name="hcm-easteurope">{{cite web |title=East-European Home-Computer: Bulgaria |url=http://www.homecomputer.de/pages/easteurope_bu.html |website=HCM: Home Computer Museum |access-date=3 October 2020 |archive-date=1 July 2006 |archive-url=https://web.archive.org/web/20060701041245/http://www.homecomputer.de/pages/easteurope_bu.html |url-status=live}}</ref>
|-
| MOS
| data-sort-value="7501"|[[MOS Technology 7501|7501]]<br/>[[MOS Technology 8501|8501]]
| 6510 (an enhanced 6502) variants, introduced in 1984.<ref name="auto">http://plus4world.powweb.com/hardware/MOS_75018501 {{Webarchive|url=https://web.archive.org/web/20200220065417/http://plus4world.powweb.com/hardware/MOS_75018501 |date=2020-02-20}} Hardware – MOS 7501/8501</ref> They extended the number of I/O port pins from 6 to 7, but omitted pins for non-maskable interrupt and clock output.<ref>https://ist.uwaterloo.ca/~schepers/MJK/7501.html {{Webarchive|url=https://web.archive.org/web/20210719064313/https://ist.uwaterloo.ca/~schepers/MJK/7501.html |date=2021-07-19}}  CPU 7501 / 8501</ref> Used in Commodore's [[Commodore 16|C-16]], [[Commodore 16|C-116]] and [[Commodore Plus/4|Plus/4]] computers. The main difference between 7501 and 8501 CPUs is that the 7501 was manufactured with the [[HMOS]]-1 process and the 8501 with HMOS-2.<ref name="auto"/>
|-
| MOS
| data-sort-value="8500"|[[MOS Technology 8500|8500]]
| Introduced in 1985 as an [[HMOS]] version of the 6510 (which is in turn based on the 6502). Other than the process modification, the 8500 is virtually identical to the [[NMOS logic|NMOS]] version of the 6510. It replaced the 6510 in later versions of the [[Commodore 64]].
|-
| MOS
| data-sort-value="8502"|[[MOS Technology 8502|8502]]
| Designed by MOS Technology and used in the [[Commodore 128]]. Based on the MOS 6510 used in the Commodore 64, the 8502 was able run at double clock rate of the 6510.<ref name="CBM128SM">''Service Manual C-128/C128D Computer'', Commodore Business Machines, PN-314001-08, November 1987</ref> The 8502 family also includes the MOS 7501, 8500 and 8501.
|-
| Hudson Soft
| data-sort-value="HuC6280"|[[Hudson Soft HuC6280|HuC6280]]
| Japanese video game company [[Hudson Soft]]'s improved version of the WDC 65C02. Manufactured for them by [[Seiko Epson]] and [[NEC]] for the [[SuperGrafx]]. The most notable product using the HuC6280 is NEC's TurboGrafx-16 video game console.
|-
| [[VLSI Technology|VLSI]]
| data-sort-value="VL65NC02"|VL65NC02<ref>{{Cite book |url=http://archive.org/details/1988_VTI_ASIC |title=IC Datasheet: 1988 VTI ASIC |pages=225–238 |chapter=VL65NC02}}</ref>
| VLSI licensed 65C02 variant was included in the [[Atari Lynx]]'s main system IC named Mikey.
|}

===16-bit derivatives===
The Western Design Center designed and, {{as of|2025|lc=on}}, still produces the [[WDC 65C816]]S processor, a 16-bit, static-core successor to the [[65C02]]. The W65C816S is a newer variant of the 65C816, which is the core of the [[Apple IIGS]] computer and is the basis of the [[Ricoh 5A22]] processor that powers the [[Super Nintendo Entertainment System]]. The W65C816S incorporates minor improvements over the 65C816 that make the newer chip not an exact hardware-compatible replacement for the earlier one. Among these improvements was conversion to a static core, which makes it possible to stop the clock in either phase without the registers losing data. Available through electronics distributors, as of March 2020, the W65C816S is officially rated for 14&nbsp;MHz operation.

The Western Design Center also designed and produced the [[WDC 65C816|65C802]], which was a 65C816 core with a 64-kilobyte address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16-bit [[accumulator (computing)|accumulator]] and [[index register]]s, and other 65C816 features. The 65C802 was not widely used and production ended.