Editing Serial Peripheral Interface (section)

==Variations==
<!-- regardless of lack of standards -->SPI implementations have a wide variety of protocol variations. Some devices are transmit-only; others are receive-only. Slave selects are sometimes active-high rather than active-low. Some devices send the least-significant bit first. Signal levels depend entirely on the chips involved. And while the baseline SPI protocol has no command codes, every device may define its own protocol of command codes. Some variations are minor or informal, while others have an official defining document and may be considered to be separate but related protocols. 

=== Original definition ===
[[Motorola]] in 1983 listed<ref>{{Cite book |url=http://archive.org/details/bitsavers_motorolada8BitMicroprocessorandPeripheralData_34048525 |title=components :: motorola :: dataBooks :: 1983 Motorola 8-Bit Microprocessor and Peripheral Data}}</ref> three [[Motorola 6805|6805]] 8-bit [[Microcomputer|microcomputers]]  that have an integrated "Serial Peripheral Interface", whose functionality is described in a 1984 manual.<ref>{{Cite book |url=http://archive.org/details/bitsavers_motoroladaSingleChipMicrocomputerData_68061538 |title=motorola :: dataBooks :: 1984 Motorola Single-Chip Microcomputer Data}}</ref>

==== AN991 ====
Motorola's 1987 Application Node AN991 "Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers"<ref>{{Cite web |title=Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers |url=http://www.bitsavers.org/components/motorola/_appNotes/AN-0991_Using_the_Serial_Peripheral_Interface_to_Communicate_between_Multiple_Microcomputers.pdf |website=[[Bitsavers]]}}</ref> (now under [[NXP Semiconductors|NXP]], last revised 2002<ref name=":4">{{cite web |date=2004 |orig-date=1994 |title=AN991/D: Using the Serial Peripheral Interface to Communicate Between Multiple Microcomputers |url=https://www.nxp.com/docs/en/application-note/AN991.pdf |url-status=live |archive-url=https://web.archive.org/web/20230404200636/https://www.nxp.com/docs/en/application-note/AN991.pdf |archive-date=2023-04-04 |access-date=2021-10-14 |website=[[NXP]]}}</ref>) informally serves as the "official" defining document for SPI.

===Timing variations===
Some devices have timing variations from Motorola's CPOL/CPHA modes. Sending data from slave to master may use the opposite clock edge as master to slave. Devices often require extra clock idle time before the first clock or after the last one, or between a command and its response.

Some devices have two clocks, one to read data, and another to transmit it into the device. Many of the read clocks run from the slave select line.

=== Transmission size ===
Different transmission word sizes are common. Many SPI chips only support messages that are multiples of 8 bits. Such chips can not interoperate with the [[JTAG]] or [[SGPIO]] protocols, or any other protocol that requires messages that are not multiples of 8 bits.

=== No slave select ===
Some devices don't use slave select, and instead manage protocol state machine entry/exit using other methods.

=== Connectors ===
Anyone needing an external connector for SPI defines their own or uses another standard connection such as: [[UEXT]], [[Pmod Interface|Pmod]], various [[JTAG connector|JTAG connectors]], [[Secure Digital]] card socket, etc.

=== Flow control ===
Some devices require an additional [[Flow control (data)|flow control]] signal from slave to master, indicating when data is ready. This leads to a 5-wire protocol instead of the usual 4. Such a ''ready'' or ''enable'' signal is often active-low, and needs to be enabled at key points such as after commands or between words. Without such a signal, data transfer rates may need to be slowed down significantly, or protocols may need to have dummy bytes inserted, to accommodate the worst case for the slave response time. Examples include initiating an ADC conversion, addressing the right page of flash memory, and processing enough of a command that device firmware can load the first word of the response. (Many SPI masters do not support that signal directly, and instead rely on fixed delays.)

=== SafeSPI ===
SafeSPI<ref>[http://SafeSPI.org SafeSPI.org]</ref> is an industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

=== High reliability modifications ===
In electrically noisy environments, since SPI has few signals, it can be economical to reduce the effects of [[common mode signal|common mode noise]] by adapting SPI to use [[low-voltage differential signaling]].<ref>{{cite web |title=Transmitting SPI over LVDS Interfaces |url=https://www.ti.com/lit/ug/tidued8/tidued8.pdf?ts=1613343608107&ref_url=https%253A%252F%252Fwww.google.com%252F |access-date=14 February 2021 |website=Texas Instruments}}</ref> Another advantage is that the controlled devices can be designed to loop-back to test signal integrity.<ref>{{cite web |title=SPI Master Loopback Example |url=https://developer.nordicsemi.com/nRF5_SDK/nRF51_SDK_v4.x.x/doc/html/group__spi__master__example.html |access-date=14 February 2021 |website=Nordic Semiconductor}}</ref>

=== Intelligent SPI controllers ===
A '''Queued Serial Peripheral Interface''' ('''QSPI'''; different to but has same abbreviation as ''Quad SPI'' described in {{Slink|2=Quad SPI|nopage=y}}) is a type of SPI controller that uses a [[queue (data structure)|data queue]] to transfer data across an SPI bus.<ref>{{Cite web |date=1996 |orig-date=1991 |title=Freescale Semiconductor, Inc. - QSM - Queued Serial Module - Reference Manual |url=https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |url-status=dead |archive-url=https://web.archive.org/web/20190824080750/https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |archive-date=2019-08-24 |website=[[NXP]]}}</ref> It has a [[circular buffer|wrap-around]] mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as [[virtual memory|memory-mapped]] parallel devices. This feature is useful in applications such as control of an [[analog-to-digital converter|A/D converter]]. Other programmable features in Queued SPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such [[direct memory access]] (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by '''Multichannel Buffered Serial Port''' ('''MCBSP''').{{NoteTag|Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. (https://www.ti.com/product/OMAP3530)}} Most SPI master controllers integrate support for up to four slave selects,{{NoteTag|Such as the SPI controller on Atmel AT91 chips like the at91sam9G20, which is much simpler than TI's McSPI.}} although some require slave selects to be managed separately through GPIO lines.

Note that ''Queued SPI'' is different from ''Quad SPI'', and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode!<ref>{{Cite web |date=2023-01-11 |title=Quad-SPI Brings Fast Parallel Data Transmission |url=https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |url-status=live |archive-url=https://web.archive.org/web/20230601194620/https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |archive-date=2023-06-01 |access-date=2023-06-30 |website=[[Cadence Design Systems]] |language=en-US}}</ref>

=== Microwire ===
Microwire,<ref>[https://www.ti.com/lit/an/snoa743/snoa743.pdf MICROWIRE Serial Interface] National Semiconductor Application Note AN-452</ref> often spelled '''μWire''', is essentially a predecessor of SPI and a trademark of [[National Semiconductor]]. It's a strict subset of SPI: half-duplex, and using SPI mode 0. Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2&nbsp;MHz vs. 20&nbsp;MHz. Some Microwire chips also support a [[Serial Peripheral Interface#Three-wire|three-wire]] mode.

=== Microwire/Plus ===
Microwire/Plus<ref>[https://www.ti.com/lit/an/snoa093/snoa093.pdf MICROWIRE/PLUS Serial Interface for COP800 Family] National Semiconductor Application Note AN-579</ref> is an enhancement of Microwire and features full-duplex communication and support for SPI modes 0 and 1. There was no specified improvement in serial clock speed.

=== Three-wire ===
Three-wire variants of SPI restricted to a [[half-duplex]] mode use a single bidirectional data line called SISO (slave out/slave in) or MOMI (master out/master in) instead of SPI's two unidirectional lines (MOSI and MISO). Three-wire tends to be used for lower-performance parts, such as small EEPROMs used only during system startup, certain sensors, and [[Serial Peripheral Interface#Microwire|Microwire]]. Few SPI controllers support this mode, although it can be easily [[Bit-banging|bit-banged]] in software.

=== Dual SPI ===
For instances where the full-duplex nature of SPI is not used, an extension uses both data pins in a half-duplex configuration to send two bits per clock cycle. Typically a command byte is sent requesting a response in dual mode, after which the MOSI line becomes SIO0 (serial I/O 0) and carries even bits, while the MISO line becomes SIO1 and carries odd bits. Data is still transmitted most-significant bit first, but SIO1 carries bits 7, 5, 3 and 1 of each byte, while SIO0 carries bits 6, 4, 2 and 0.

This is particularly popular among SPI ROMs, which have to send a large amount of data, and comes in two variants:<ref name="W25Q16JV">{{cite web |title=W25Q16JV 3V 16M-bit serial flash memory with Dual/Quad SPI |date=12 August 2016 |version=Revision D |publisher=[[Winbond]] |type=data sheet |url=https://www.winbond.com/resource-files/w25q16jv%20spi%20revd%2008122016.pdf |access-date=2017-02-10}}</ref><ref name="D25LQ64">{{cite web |title=D25LQ64 1.8V Uniform Sector Dual and Quad SPI Flash |type=data sheet |date=11 February 2011 |version=version 0.1 |publisher=GigaDevice |url=https://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |archive-url=https://web.archive.org/web/20170212090900/http://www.sst-ic.com/File/DataSheet/KC909742-1112151725544ed0c4ce-8225-4c46-8d18-b81422086247.pdf |url-status=dead |archive-date=12 February 2017 |access-date=2017-02-10}}</ref>

* Dual read sends the command and address from the master in single mode, and returns the data in dual mode.
* Dual I/O sends the command in single mode, then sends the address and return data in dual mode.

=== Quad SPI ===
'''Quad SPI''' ('''QSPI'''; different to but has same abbreviation as ''Queued-SPI'' described in {{Slink|2=Intelligent SPI controllers|nopage=y}}) goes beyond dual SPI, adding two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. Again, it is requested by special commands, which enable quad mode after the command itself is sent in single mode.{{r|W25Q16JV|D25LQ64}}

; SQI Type 1: Commands sent on single line but addresses and data sent on four lines
; SQI Type 2: Commands and addresses sent on a single line but data sent/received on four lines

=== QPI/SQI ===
Further extending quad SPI, some devices support a "quad everything" mode where ''all'' communication takes place over 4 data lines, including commands.<ref>{{cite web |url=https://community.nxp.com/thread/336422 |title=QuadSPI flash: Quad SPI mode vs. QPI mode |date=December 2014 |website=NXP community forums |access-date=2016-02-10}}</ref>   This is variously called "QPI"{{r|D25LQ64}} (not to be confused with [[Intel QuickPath Interconnect]]) or "serial quad I/O" (SQI)<ref name="SST26VF032B">{{cite web |title=SST26VF032B / SST26VF032BA 2.5V/3.0V 32 Mbit Serial Quad I/O (SQI) Flash Memory |type=Data sheet |publisher=[[Microchip, Inc.]] |date=2017 |version=version E |url=http://ww1.microchip.com/downloads/en/DeviceDoc/20005218E.pdf |access-date=2017-02-10}}</ref>

This requires programming a configuration bit in the device and requires care after reset to establish communication.

=== Double data rate ===
In addition to using multiple lines for I/O, some devices increase the transfer rate by using [[double data rate]] transmission.<ref>{{Cite web |first=David |last=Patterson |url=https://www.nxp.com/files/32bit/doc/app_note/AN4512.pdf |title=Quad Serial Peripheral Interface (QuadSPI) Module Updates |type=Application note |date=May 2012 |access-date=September 21, 2016 |publisher=[[Freescale Semiconductor]]}}</ref><ref>{{cite news |title=Improving performance using SPI-DDR NOR flash memory |first=Rich |last=Pell |date=13 October 2011 |journal=[[EDN (magazine)|EDN]] |url=https://www.edn.com/design/systems-design/4368499/Improving-performance-using-SPI-DDR-NOR-flash-memory-4368499}}</ref>

=== JTAG ===
{{Main articles|JTAG}}
Although there are some similarities between SPI and the [[JTAG]] (IEEE 1149.1-2013) protocol, they are not interchangeable. JTAG is specifically intended to provide reliable [[Boundary scan|test access to the I/O pins]] from an off-board controller with less precise signal delay and skew parameters, while SPI has many varied applications. While not strictly a level sensitive interface, the JTAG protocol supports the recovery of both setup and hold violations between JTAG devices by reducing the clock rate or changing the clock's duty cycles. Consequently, the JTAG interface is not intended to support extremely high data rates.<ref>IEEE 1149.1-2013</ref>

=== SGPIO ===
{{Main articles|SGPIO}}
[[SGPIO]] is essentially another (incompatible) application stack for SPI designed for particular backplane management activities.{{citation needed|date=July 2010}} SGPIO uses 3-bit messages.

===Intel's Enhanced Serial Peripheral Interface===
[[Intel]] has developed a successor to its [[Low Pin Count]] (LPC) bus that it calls the '''Enhanced Serial Peripheral Interface (eSPI)''' bus. Intel aims to reduce the number of pins required on motherboards and increase throughput compared to LPC, reduce the working voltage to 1.8 volts to facilitate smaller chip manufacturing processes, allow eSPI peripherals to share SPI flash devices with the host (the LPC bus did not allow firmware hubs to be used by LPC peripherals), tunnel previous [[Out-of-band signal|out-of-band]] pins through eSPI, and allow system designers to trade off cost and performance.<ref name="eSPI">{{cite report |title=Enhanced Serial Peripheral Interface (eSPI) Interface Base Specification (for Client and Server Platforms) |date=January 2016 |version=Revision 1.0 |url=https://www-ssl.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0_cb.pdf |publisher=Intel |access-date=2017-02-05 |id=Document number 327432-004}}</ref><ref>{{cite report |id=Document Number 327432-001EN |title=Enhanced Serial Peripheral Interface (eSPI) Interface Specification (for Client Platforms) |date=May 2012 |version=Revision 0.6 |url=https://downloadmirror.intel.com/21353/eng/eSPI%20Specification%20rev0.6%20(client).pdf |publisher=Intel |access-date=2017-02-05}}</ref>

An eSPI bus can either be shared with SPI devices to save pins or be separate from an SPI bus to allow more performance, especially when eSPI devices need to use SPI flash devices.<ref name="eSPI" />

This standard defines an Alert# signal that is used by an eSPI slave to request service from the master. In a performance-oriented design or a design with only one eSPI slave, each eSPI slave will have its Alert# pin connected to an Alert# pin on the eSPI master that is dedicated to each slave, allowing the eSPI master to grant low-latency service, because the eSPI master will know which eSPI slave needs service and will not need to poll all of the slaves to determine which device needs service. In a budget design with more than one eSPI slave, all of the Alert# pins of the slaves are connected to one Alert# pin on the eSPI master in a [[wired-OR]] connection, which requires the master to poll all the slaves to determine which ones need service when the Alert# signal is pulled low by one or more peripherals that need service. Only after all of the devices are serviced will the Alert# signal be pulled high due to none of the eSPI slaves needing service and therefore pulling the Alert# signal low.<ref name="eSPI" />

This standard allows designers to use 1-bit, 2-bit, or 4-bit communications at speeds from 20 to 66&nbsp;MHz to further allow designers to trade off performance and cost.<ref name="eSPI" />

Communications that were out-of-band of LPC like [[general-purpose input/output]] (GPIO) and [[System Management Bus]] (SMBus) should be tunneled through eSPI via virtual wire cycles and out-of-band message cycles respectively in order to remove those pins from motherboard designs using eSPI.<ref name="eSPI" />

This standard supports standard memory cycles with lengths of 1 byte to 4 kilobytes of data, short memory cycles with lengths of 1, 2, or 4 bytes that have much less overhead compared to standard memory cycles, and I/O cycles with lengths of 1, 2, or 4 bytes of data which are low overhead as well. This significantly reduces overhead compared to the LPC bus, where all cycles except for the 128-byte firmware hub read cycle spends more than one-half of all of the bus's throughput and time in overhead. The standard memory cycle allows a length of anywhere from 1 byte to 4 kilobytes in order to allow its larger overhead to be amortised over a large transaction. eSPI slaves are allowed to initiate bus master versions of all of the memory cycles. Bus master I/O cycles, which were introduced by the LPC bus specification, and ISA-style DMA including the 32-bit variant introduced by the LPC bus specification, are not present in eSPI. Therefore, bus master memory cycles are the only allowed DMA in this standard.<ref name="eSPI" />

eSPI slaves are allowed to use the eSPI master as a proxy to perform flash operations on a standard SPI flash memory slave on behalf of the requesting eSPI slave.<ref name="eSPI" />

64-bit memory addressing is also added, but is only permitted when there is no equivalent 32-bit address.<ref name="eSPI" />

The Intel [[Z170|Z170 chipset]] can be configured to implement either this bus or a variant of the LPC bus that is missing its ISA-style DMA capability and is underclocked to 24&nbsp;MHz instead of the standard 33&nbsp;MHz.<ref>{{Cite web | url = https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/100-series-chipset-datasheet-vol-1.pdf | title = Intel® 100 Series Chipset Family PCH Datasheet, Vol. 1 | access-date = April 15, 2015}}</ref>

The eSPI bus is also adopted by [[AMD Ryzen]] chipsets.