Editing Static random-access memory (section)

===Reading===
In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a single access transistor and bit line, e.g. M<sub>6</sub>, BL. However, bit lines are relatively long and have large [[parasitic capacitance]]. To speed up reading, a more complex process is used in practice: The read cycle is started by precharging both bit lines BL and <span style="text-decoration: overline;">BL</span>, to high (logic '''1''') voltage. Then asserting the word line WL enables both the access transistors M<sub>5</sub> and M<sub>6</sub>, which causes one bit line BL voltage to slightly drop. Then the BL and <span style="text-decoration: overline;">BL</span> lines will have a small voltage difference between them. A sense amplifier will sense which line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read operation. As the NMOS is more powerful, the pull-down is easier. Therefore, bit lines are traditionally precharged to high voltage. Many researchers are also trying to precharge at a slightly low voltage to reduce the power consumption.<ref>{{Cite journal|url=https://www.tandfonline.com/doi/full/10.1080/1023697X.2014.970761|title=SRAM precharge system for reducing write power|first1=Hussain Mohammed Dipu|last1=Kabir|first2=Mansun|last2=Chan|date=January 2, 2015|journal=HKIE Transactions|volume=22|issue=1|pages=1–8|via=CrossRef|doi=10.1080/1023697X.2014.970761|s2cid=108574841 |url-access=subscription}}</ref><ref>{{Cite web|url=https://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.119.3735|title=CiteSeerX|website=CiteSeerX|citeseerx=10.1.1.119.3735 }}</ref>