Editing 3DNow! (section)

==Versions==

===3DNow!===
The first implementation of 3DNow! technology contains 21 new instructions that support [[SIMD]] floating-point operations. The 3DNow! data format is packed, [[single-precision]], floating-point. The 3DNow! instruction set also includes operations for SIMD integer operations, data prefetch, and faster MMX-to-floating-point switching. Later, [[Intel]] would add similar (but incompatible) instructions to the [[Pentium III]], known as [[Streaming SIMD Extensions|SSE]] (Streaming SIMD Extensions).

3DNow! floating-point instructions are the following:
{{Div col|colwidth=30em}}
* <code>PI2FD</code>{{snd}} Packed 32-bit integer to floating-point conversion
* <code>PF2ID</code>{{snd}} Packed floating-point to 32-bit integer conversion
* <code>PFCMPGE</code>{{snd}} Packed floating-point comparison, greater or equal
* <code>PFCMPGT</code>{{snd}} Packed floating-point comparison, greater
* <code>PFCMPEQ</code>{{snd}} Packed floating-point comparison, equal
* <code>PFACC</code>{{snd}} Packed floating-point accumulate
* <code>PFADD</code>{{snd}} Packed floating-point addition
* <code>PFSUB</code>{{snd}} Packed floating-point subtraction
* <code>PFSUBR</code>{{snd}} Packed floating-point reverse subtraction
* <code>PFMIN</code>{{snd}} Packed floating-point minimum
* <code>PFMAX</code>{{snd}} Packed floating-point maximum
* <code>PFMUL</code>{{snd}} Packed floating-point multiplication
* <code>PFRCP</code>{{snd}} Packed floating-point reciprocal approximation
* <code>PFRSQRT</code>{{snd}} Packed floating-point reciprocal square root approximation
* <code>PFRCPIT1</code>{{snd}} Packed floating-point reciprocal, first iteration step
* <code>PFRSQIT1</code>{{snd}} Packed floating-point reciprocal square root, first iteration step
* <code>PFRCPIT2</code>{{snd}} Packed floating-point reciprocal/reciprocal square root, second iteration step
{{div col end}}

3DNow! integer instructions are the following:
* <code>PAVGUSB</code>{{snd}} Packed 8-bit unsigned integer averaging
* <code>PMULHRW</code>{{snd}} Packed 16-bit integer multiply with rounding

3DNow! performance-enhancement instructions are the following:
* <code>FEMMS</code>{{snd}} Faster entry/exit of the MMX or floating-point state
* <code>PREFETCH/PREFETCHW</code>{{snd}} Prefetch at least a 32-byte line into L1 data cache (this is the only non-deprecated instruction)

===3DNow! extensions===
There is little or no evidence that the second version of 3DNow! was ever officially given its own trade name. This has led to some confusion in documentation that refers to this new instruction set. The most common terms are ''Extended 3DNow!'', ''Enhanced 3DNow!'' and ''3DNow!+''. The phrase "Enhanced 3DNow!" can be found in a few locations on the AMD website but the capitalization of "Enhanced" appears to be either purely grammatical or used for emphasis on processors that may or may not have these extensions (the most notable of which references a benchmark page for the K6-III-P that does not have these extensions).<ref name="extman">{{cite web
|url=https://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
|title=AMD Extensions to the 3DNow and MMX Instruction Sets Manual
|publisher=[[Advanced Micro Devices, Inc.]]
|date=March 2000
|access-date=2008-06-07
|archive-date=2008-05-17
|archive-url=https://web.archive.org/web/20080517014932/http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
|url-status=live
}}</ref><ref>{{cite web
|url=https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_1300%5E960,00.html
|title=Mobile AMD-K6-III-P Processor-Based Notebook: Ziff-Davis CPUmark 99
|quote=Incorrect title on page: Mobile AMD-K6-III+ and Mobile AMD-K6-2+ Processors with Enchanced {{sic}} 3DNow! Technology
|access-date=2008-06-07
|archive-date=2008-07-24
|archive-url=https://web.archive.org/web/20080724223037/http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_1300%5E960,00.html
|url-status=live
}}</ref>

This extension to the 3DNow! instruction set was introduced with the first-generation [[Athlon]] processors. The Athlon added five new 3DNow! instructions and 19 new MMX instructions. Later, the [[AMD K6-2|K6-2+]] and [[AMD K6-III|K6-III+]] (both targeted at the mobile market) included the five new 3DNow! instructions, leaving out the 19 new MMX instructions. The new 3DNow! instructions were added to boost [[Digital signal processing|DSP]]. The new MMX instructions were added to boost [[streaming media]].

The 19 new MMX instructions are a subset of Intel's SSE instruction set. In AMD technical manuals, AMD segregates these instructions apart from the 3DNow! extensions.<ref name="extman"/> In AMD customer product literature, however, this segregation is less clear where the benefits of all 24 new instructions are credited to enhanced 3DNow! technology.<ref>{{cite web
|url=https://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_759%5E1151,00.html
|title=AMD Athlon Processor Product Brief
|publisher=[[Advanced Micro Devices, Inc.]]
|access-date=2008-06-08
|archive-date=2008-02-25
|archive-url=https://web.archive.org/web/20080225111905/http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_759%5E1151,00.html
|url-status=live
}}</ref> This has led programmers to come up with their own name for the 19 new MMX instructions. The most common appears to be ''Integer SSE'' (''ISSE'').<ref>{{cite web
|url=http://avisynth.nl/index.php/ISSE
|title=ISSE
|website=[[AviSynth]]
|access-date=2017-07-19
|archive-date=2017-07-02
|archive-url=https://web.archive.org/web/20170702204448/http://avisynth.nl/index.php/ISSE
|url-status=live
}}</ref> ''SSEMMX'' and ''MMX2'' are also found in video filter documentation from the public domain sector. ISSE could also refer to Internet SSE, an early name for SSE.

3DNow! extension DSP instructions are the following:
* <code>PF2IW</code>{{snd}} Packed floating-point to integer word conversion with sign extend
* <code>PI2FW</code>{{snd}} Packed integer word to floating-point conversion
* <code>PFNACC</code>{{snd}} Packed floating-point negative accumulate
* <code>PFPNACC</code>{{snd}} Packed floating-point mixed positive-negative accumulate
* <code>PSWAPD</code>{{snd}} Packed swap doubleword

MMX extension instructions (Integer SSE) are the following:
{{Div col|colwidth=30em}}
* <code>MASKMOVQ</code>{{snd}} Streaming (cache bypass) store using byte mask
* <code>MOVNTQ</code>{{snd}} Streaming (cache bypass) store
* <code>PAVGB</code>{{snd}} Packed average of unsigned byte
* <code>PAVGW</code>{{snd}} Packed average of unsigned word
* <code>PMAXSW</code>{{snd}} Packed maximum signed word
* <code>PMAXUB</code>{{snd}} Packed maximum unsigned byte
* <code>PMINSW</code>{{snd}} Packed minimum signed word
* <code>PMINUB</code>{{snd}} Packed minimum unsigned byte
* <code>PMULHUW</code>{{snd}} Packed multiply high unsigned word
* <code>PSADBW</code>{{snd}} Packed sum of absolute byte differences
* <code>PSHUFW</code>{{snd}} Packed shuffle word
* <code>PEXTRW</code>{{snd}} Extract word into integer register
* <code>PINSRW</code>{{snd}} Insert word from integer register
* <code>PMOVMSKB</code>{{snd}} Move byte mask to integer register
* <code>PREFETCHNTA</code>{{snd}} Prefetch using the NTA reference
* <code>PREFETCHT0</code>{{snd}} Prefetch using the T0 reference
* <code>PREFETCHT1</code>{{snd}} Prefetch using the T1 reference
* <code>PREFETCHT2</code>{{snd}} Prefetch using the T2 reference
* <code>SFENCE</code>{{snd}} Store fence
{{div col end}}

===3DNow! Professional===
''3DNow! Professional'' is a trade name used to indicate processors that combine 3DNow! technology with a complete SSE instructions set (such as SSE, SSE2 or SSE3).<ref>{{cite web
 |url=https://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_4513%5E1413%5E2137,00.html 
 |title=Explaining the new 3DNow! Professional Technology 
 |publisher=[[Advanced Micro Devices, Inc.]] 
 |access-date=2008-06-08 
 |url-status=dead 
 |archive-url=https://web.archive.org/web/20090121005440/http://www.amd.com/us-en/Processors/SellAMDProducts/0%2C%2C30_177_4458_4513%5E1413%5E2137%2C00.html 
 |archive-date=2009-01-21 
}}</ref> The [[Athlon XP]] was the first processor to carry the 3DNow! Professional trade name, and was the first product in the Athlon family to support the complete SSE instruction set (for the total of: 21 original 3DNow! instructions; five 3DNow! extension DSP instructions; 19 MMX extension instructions; and 52 additional SSE instructions for complete SSE compatibility).<ref>{{cite web
|url=https://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505%5E3785%5E3738,00.html
|title=AMD Athlon XP Architectural Features
|publisher=[[Advanced Micro Devices, Inc.]]
|access-date=2008-06-08
|archive-date=2008-02-25
|archive-url=https://web.archive.org/web/20080225112033/http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505%5E3785%5E3738,00.html
|url-status=live
}}</ref>

===3DNow! and the Geode GX/LX===
The [[Geode (processor)|Geode GX and Geode LX]] added two new 3DNow! instructions which is absent in all other processors.

3DNow! "professional" instructions unique to the Geode GX/LX are the following:
* <code>PFRSQRTV</code>{{snd}} Reciprocal square root approximation for a pair of 32-bit floats
* <code>PFRCPV</code>{{snd}} Reciprocal approximation for a pair of 32-bit floats