Editing AVR microcontrollers (section)

== Device overview ==
The AVR is a modified Harvard architecture machine, where program and data are stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.

=== Basic families ===
AVRs are generally classified into following:

'''tinyAVR''' – the ATtiny series
{{Main|ATtiny microcontroller comparison chart}}

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
|- align="right"
| 0.5–32 KB
| 1.6–20
| 6–32-pin package
| 32–3072 bytes
| 64–512 bytes
|}

The ATtiny series features small package microcontrollers with a limited peripheral set available. However, the improved tinyAVR 0/1/2-series (released in 2016) include: 
* Peripherals equal to or exceed megaAVR 0-series
* Event System
* Improved AVRxt instruction set (improved timing of calls), hardware multiply

'''megaAVR''' – the ATmega series

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
|- align="right"
| 4–256 KB
| 1.6–20
| 28–100-pin package
| 256–16384 bytes
| 256–4096 bytes
|}

The ATmega series features microcontrollers that provide an extended instruction set (multiply instructions and instructions for handling larger program memories), an extensive peripheral set, a solid amount of program memory, as well as a wide range of pins available. The megaAVR 0-series (released in 2016) also has functionality such as: 
* Event system
* New peripherals with enhanced functionality
* Improved AVRxt instruction set (improved timing of calls)

'''AVR Dx''' – The AVR Dx family features multiple microcontroller series, focused on [[human–computer interaction|HCI]], analog signal conditioning and functional safety.

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
! Release year
|- align="right"
| 16–128 KB
| 20–24 at 1.8–5.5&nbsp;V
| 14–64-pin package
| 4–16 KB
| 512 bytes
| 2020
|}

The parts numbers is formatted as AVR''ff''D''xpp'', where ''ff'' is flash size, ''x'' is family, and ''pp'' is number of pins. Example: AVR128DA64 – 64-pin DA-series with 128k flash. All devices in the AVR Dx family include: 
* an Async Type D timer that can run faster than the CPU
* 12-bit ADC
* 10-bit DAC
* '''AVR DA-series''' (early 2020) – The high memory density makes these MCUs well suited for both wired and wireless communication-stack-intensive functions.
** integrated sensors for capacitative touch measurement ([[Human–computer interaction|HCI]])
** updated core independent peripherals ([[Autonomous peripheral operation|CIPs]]) and analog peripherals
** no external high frequency crystal
* '''AVR DB-series''' (mid-late 2020) – inherits many features from the DA-family, while adding its own:
** 2 or 3 on-chip opamps
** MultiVoltage IO (MVIO) on PORTC
** Supports external HF crystal
* '''AVR DD-series'''
** 16–64 KiB Flash
** 2–8 KiB SRAM
** 14–32-pin package
** internal 24&nbsp;MHz oscillator
** 7–23-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)
** no amplifiers
** 1 analog comparator
** Two  USARTs, one SPI, one dual-mode TWI
** Multi-Voltage Input/Output (MVIO) support on 3 or 4 pins on Port C
** 4 Configurable Custom Logic (CCL) cells, 6 Event System channels
* '''AVR EA-series'''
** 8–64 KiB Flash
** 28–48-pin package
** internal 20&nbsp;MHz oscillator
** 24–32-channel 130 kS/s 12-bit differential Analog-to-Digital Converter (ADC)
** Programmable Gain Amplifier (PGA) with up to 16x gain
** 2 analog comparators
** Three USARTs, one SPI, one dual-mode TWI
** no Multi-Voltage Input/Output (MVIO)
** 4 Configurable Custom Logic (CCL) cells, 6 Event System channels

'''XMEGA'''

{| class="wikitable"
! [[Flash memory|Flash size]]
! Frequency<br />[MHz]
! [[Chip carrier|Package]]
! [[Static random-access memory|SRAM]]
! [[EEPROM]]
! Release year
|- align="right"
| 16–256 KB
| 32
| 44–100-pin package
| 1–32 KB
| 512–2048 bytes
| — 
|}

the ATxmega series offers a wide variety of peripherals and functionality such as:
* Extended performance features, such as DMA, "Event System", and cryptography support
* Extensive peripheral set with [[Analog-to-digital converter|ADCs]]

'''Application-specific AVR'''
* megaAVRs with special features not found on the other members of the AVR family, such as LCD controller, [[Universal Serial Bus|USB]] controller, advanced PWM, CAN, etc.

'''FPSLIC (AVR with FPGA)'''
* [[Field-programmable gate array|FPGA]] 5k to 40k gates
* SRAM for the AVR program code, unlike all other AVRs
* AVR core can run at up to 50&nbsp;MHz<ref>[http://www.atmel.com/products/other/field_programmable_gate_array/default.aspx Field Programmable System Level Integrated Circuit]. {{webarchive|url=https://web.archive.org/web/20121127102202/http://www.atmel.com/products/other/field_programmable_gate_array/default.aspx|date=2012-11-27}}.</ref>

'''32-bit AVRs'''{{Main|AVR32}}
* In 2006, Atmel released microcontrollers based on the 32-bit [[AVR32]] architecture. This was a completely different architecture unrelated to the 8-bit AVR, intended to compete with the [[ARM architecture|ARM]]-based processors. It had a 32-bit data path, [[SIMD]] and [[Digital signal processor|DSP]] instructions, along with other audio- and video-processing features. The instruction set was similar to other RISC cores, but it was not compatible with the original AVR (nor any of the various ARM cores). Since then support for AVR32 has been dropped from Linux as of kernel 4.12; compiler support for the architecture in [[GNU Compiler Collection|GCC]] was never mainlined into the compiler's central source-code repository and was available primarily in a vendor-supported fork. At the time that AVR32 was introduced, Atmel had already been a licensee of the [[ARM architecture]], with both [[ARM7]] and [[ARM9]] microcontrollers having been released prior to and concurrently with the AVR32; later Atmel focused most development effort on 32-bit chips with [[ARM Cortex-M]] and [[ARM Cortex-A|Cortex-A]] cores.

=== Device architecture ===
[[File:AVR_ATXMEGA_128A1.JPG|right|thumb|Atmel ATxmega128A1 in 100-pin [[TQFP]] package]]
[[File:ATMEL MEGA32U4 (Micro Controller).png|thumb|ATMEL MEGA32U4 die shot]]
The AVRs have 32 [[Byte|single-byte]] [[Processor register|registers]] and are classified as 8-bit RISC devices.

[[Flash memory|Flash]], [[EEPROM]], and [[Static random-access memory|SRAM]] are all integrated onto a single chip, removing the need for external memory in most applications. Some devices have a parallel external bus option to allow adding additional data memory or memory-mapped devices. Almost all devices (except the smallest TinyAVR chips) have serial interfaces, which can be used to connect larger serial EEPROMs or flash chips.

==== Program memory ====
Program instructions are stored in [[non-volatile]] [[flash memory]]. Although the [[Microcontroller unit|MCUs]] are 8-bit, each instruction takes one or two 16-bit words. The size of the program memory is usually indicated in the naming of the device itself (e.g., the ATmega64x line has 64&nbsp;KB of flash, while the ATmega32x line has 32&nbsp;KB). There is no provision for off-chip program memory; all code executed by the AVR core must reside in the on-chip flash. However, this limitation does not apply to the AT94 FPSLIC AVR/FPGA chips.

==== Internal data memory ====
The data [[address space]] consists of the [[register file]], I/O registers, and [[Static random-access memory|SRAM]]. Some small models also map the program ROM into the data address space, but larger models do not.

==== Internal registers ====
In the tinyAVR and megaAVR variants of the [[Atmel AVR instruction set|AVR architecture]], the working registers are mapped in as the first 32 data memory addresses (0000<sub>16</sub>–001F<sub>16</sub>), followed by 64 I/O registers (0020<sub>16</sub>–005F<sub>16</sub>). In devices with many peripherals, these registers are followed by 160 “extended I/O” registers, only accessible as [[memory-mapped I/O]] (0060<sub>16</sub>–00FF<sub>16</sub>).

Actual SRAM starts after these register sections, at address 0060<sub>16</sub> or, in devices with "extended I/O", at 0100<sub>16</sub>.

Even though there are separate addressing schemes and optimized opcodes for accessing the register file and the first 64 I/O registers, all can also be addressed and manipulated as if they were in SRAM.

The very smallest of the tinyAVR variants use a reduced architecture with only 16 registers (r0 through r15 are omitted) which are not addressable as memory locations. I/O memory begins at address 0000<sub>16</sub>, followed by SRAM. In addition, these devices have slight deviations from the standard AVR instruction set. Most notably, the direct load/store instructions (LDS/STS) have been reduced from 2 words (32 bits) to 1 word (16 bits), limiting the total direct addressable memory (the sum of both I/O and SRAM) to 128 bytes. Conversely, the indirect load instruction's (LD) 16-bit address space is expanded to also include non-volatile memory such as Flash and configuration bits; therefore, the Load Program Memory (LPM) instruction is unnecessary and omitted. (For detailed info, see [[Atmel AVR instruction set]].)

In the XMEGA variant, the working register file is not mapped into the data address space; as such, it is not possible to treat any of the XMEGA's working registers as though they were SRAM. Instead, the I/O registers are mapped into the data address space starting at the very beginning of the address space. Additionally, the amount of data address space dedicated to I/O registers has grown substantially to 4096 bytes (0000<sub>16</sub>–0FFF<sub>16</sub>). As with previous generations, however, the fast I/O manipulation instructions can only reach the first 64 I/O register locations (the first 32 locations for bitwise instructions). Following the I/O registers, the XMEGA series sets aside a 4096 byte range of the data address space, which can be used optionally for mapping the internal EEPROM to the data address space (1000<sub>16</sub>–1FFF<sub>16</sub>). The actual SRAM is located after these ranges, starting at 2000<sub>16</sub>.

==== General-purpose input/output (GPIO) ports ====
Each [[GPIO]] port on a tiny or mega AVR drives up to eight pins and is controlled by three 8-bit registers: DDR''x'', PORT''x'' and PIN''x'', where ''x'' is the port identifier.

* DDR''x'': Data Direction Register, configures the pins as either inputs or outputs.
* PORT''x'': Output port register. Sets the output value on pins configured as outputs. Enables or disables the [[pull-up resistor]] on pins configured as inputs.
* PIN''x'': Input register, used to read an input signal. On some devices, this register can be used for pin toggling: writing a logic one to a PIN''x'' bit toggles the corresponding bit in PORT''x'', irrespective of the setting of the DDR''x'' bit.<ref>[http://www.atmel.com/Images/Atmel-2586-AVR-8-bit-Microcontroller-ATtiny25-ATtiny45-ATtiny85_Datasheet.pdf atmel.com]</ref>

Newer ATtiny AVRs, like ATtiny817 and its siblings, have their port control registers somewhat differently defined.
xmegaAVR have additional registers for push/pull, totem-pole and pullup configurations.

==== EEPROM ====
Almost all AVR microcontrollers have internal [[EEPROM]] for semi-permanent data storage. Like flash memory, EEPROM can maintain its contents when electrical power is removed.

In most variants of the AVR architecture, this internal EEPROM memory is not mapped into the MCU's addressable memory space. It can only be accessed the same way an external peripheral device is, using special pointer registers and read/write instructions, which makes EEPROM access much slower than other internal RAM.

However, some devices in the SecureAVR (AT90SC) family<ref>[http://www.atmel.com/images/doc1010.pdf Atmel Smart Card ICs]</ref> use a special EEPROM mapping to the data or program memory, depending on the configuration. The XMEGA family also allows the EEPROM to be mapped into the data address space.

Since the number of writes to EEPROM is limited{{snd}} Atmel specifies 100,000 write cycles in their datasheets{{snd}} a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed.

=== Program execution ===
Atmel's AVRs have a two-stage, single-level [[Pipeline (computing)|pipeline]] design, meaning that the next machine instruction is fetched as the current one is executing. Most instructions take just one or two clock cycles, making AVRs relatively fast among [[eight-bit]] microcontrollers.

The AVR processors were designed with the efficient execution of [[Compiler|compiled]] [[C (programming language)|C]] code in mind and have several built-in pointers for the task.

=== Instruction set ===
{{Main|Atmel AVR instruction set}}
The [[Atmel AVR instruction set|AVR instruction set]] is more [[Orthogonal instruction set|orthogonal]] than those of most eight-bit microcontrollers, in particular the [[Intel 8051|8051 clones]] and [[PIC microcontroller]]s with which AVR has competed. However, it is not completely regular:

* [[Pointer register]]s X, Y, and Z have addressing capabilities that are different from each other.
* [[Processor register|Register]] locations R0 to R15 have more limited addressing capabilities than register locations R16 to R31.
* I/O ports 0 to 31 can be bit addressed, unlike I/O ports 32 to 63.
* CLR (clear all bits to zero) affects flags, while SER (set all bits to one) does not, even though they are complementary instructions. (CLR is pseudo-op for EOR R, R; while SER is short for LDI R,$FF. Arithmetic operations such as EOR modify flags, while moves/loads/stores/branches such as LDI do not.)
* Accessing read-only data stored in the program memory (flash) requires special LPM instructions; the flash bus is otherwise reserved for instruction memory.

Some chip-specific differences affect code generation. Code pointers (including return addresses on the stack) are two bytes long on chips with up to 128&nbsp;KB of flash memory, but three bytes long on larger chips; not all chips have hardware multipliers; chips with over 8&nbsp;KB of flash have branch and call instructions with longer ranges; and so forth.

The mostly regular instruction set makes C (and even Ada) compilers fairly straightforward and efficient. [[GNU Compiler Collection|GCC]] has included AVR support for quite some time, and that support is widely used. [[LLVM]] also has rudimentary AVR support. In fact, Atmel solicited input from major developers of compilers for small microcontrollers, to determine the instruction set features that were most useful in a compiler for high-level languages.<ref name="codesign" />

=== MCU speed ===
The AVR line can normally support clock speeds from 0 to 20&nbsp;MHz, with some devices reaching 32&nbsp;MHz. Lower-powered operation usually requires a reduced clock speed. All recent (Tiny, Mega, and Xmega, but not 90S) AVRs feature an on-chip oscillator, removing the need for external clocks or resonator circuitry. Some AVRs also have a system clock prescaler that can divide down the system clock by up to 1024. This prescaler can be reconfigured by software during run-time, allowing the clock speed to be optimized.

Since all operations (excluding multiplication and 16-bit add/subtract) on registers R0–R31 are single-cycle, the AVR can achieve up to 1 [[Million instructions per second|MIPS]] per MHz, i.e. an 8&nbsp;MHz processor can achieve up to 8&nbsp;MIPS. Loads and stores to/from memory take two cycles, branching takes two cycles. Branches in the latest "3-byte PC" parts such as ATmega2560 are one cycle slower than on previous devices.

=== Development ===
AVRs have a large following due to the free and inexpensive development tools available, including reasonably priced development boards and free development software. The AVRs are sold under various names that share the same basic core, but with different peripheral and memory combinations. Compatibility between chips in each family is fairly good, although I/O controller features may vary.

See [[#External links|external links]] for sites relating to AVR development.

=== Features ===
AVRs offer a wide range of features:

* Multifunction, bi-directional general-purpose I/O ports with configurable, built-in [[pull-up resistor]]s
* Multiple internal oscillators, including RC oscillator without external parts
* Internal, self-programmable instruction [[flash memory]] up to 256&nbsp;KB (384&nbsp;KB on XMega)
** [[In-system programming|In-system programmable]] using serial/parallel low-voltage proprietary interfaces or [[JTAG]]
** Optional boot code section with independent lock bits for protection
* On-chip debugging (OCD) support through JTAG or [[debugWIRE]] on most devices
** The JTAG signals (TMS, TDI, TDO, and TCK) are multiplexed on [[General Purpose Input/Output|GPIOs]]. These pins can be configured to function as JTAG or GPIO depending on the setting of a [[fuse bit]], which can be programmed via [[in-system programming]] (ISP) or HVSP. By default, AVRs with JTAG come with the JTAG interface enabled.
** [[debugWIRE]] uses the /RESET pin as a bi-directional communication channel to access on-chip debug circuitry. It is present on devices with lower pin counts, as it only requires one pin.
* Internal data [[EEPROM]] up to 4&nbsp;KB
* Internal [[Static random-access memory|SRAM]] up to 16&nbsp;KB (32&nbsp;KB on XMega)
* External 64&nbsp;KB little endian data space on certain models, including the Mega8515 and Mega162.
** The external data space is overlaid with the internal data space, such that the full 64&nbsp;KB address space does not appear on the external bus and accesses to e.g. address 0100<sub>16</sub> will access internal RAM, not the external bus.
** In certain members of the XMega series, the external data space has been enhanced to support both SRAM and SDRAM. As well, the data addressing modes have been expanded to allow up to 16&nbsp;MB of data memory to be directly addressed.
* 8-bit and 16-bit timers
** [[Pulse-width modulation|PWM]] output (some devices have an enhanced PWM peripheral which includes a dead-time generator)
** Input capture that record a time stamp triggered by a signal edge
* analog comparator
* 10 or 12-bit [[Analog-to-digital converter|A/D converters]], with multiplex of up to 16 channels
* 12-bit [[Digital-to-analog converter|D/A converters]]
* A variety of serial interfaces, including
** [[I²C]] compatible Two-Wire Interface (TWI)
** Synchronous/asynchronous serial peripherals ([[Universal asynchronous receiver/transmitter|UART]]/USART) (used with [[RS-232]], [[RS-485]], and more)
** [[Serial Peripheral Interface Bus]] (SPI)
** Universal Serial Interface (USI): a multi-purpose hardware communication module that can be used to implement an SPI,<ref>{{cite web|url=http://www.atmel.com/images/doc2582.pdf |archive-url=https://web.archive.org/web/20120617084714/http://www.atmel.com/images/doc2582.pdf |archive-date=2012-06-17 |url-status=live|title=AVR319: Using the USI module for SPI communication|date=2004|publisher=[[Atmel]]|access-date=10 June 2014}}</ref> I<sup>2</sup>C<ref>{{cite web|url=http://www.atmel.com/images/atmel-2561-using-the-usi-module-as-a-i2c-master_ap-note_avr310.pdf |archive-url=https://web.archive.org/web/20140714124026/http://www.atmel.com/images/atmel-2561-using-the-usi-module-as-a-i2c-master_ap-note_avr310.pdf |archive-date=2014-07-14 |url-status=live|title=Atmel AVR310: Using the USI Module as a I<sup>2</sup>C Master|date=2013|publisher=[[Atmel]]|access-date=10 June 2014}}</ref><ref>{{cite web|url=http://www.atmel.com/Images/doc2560.pdf |archive-url=https://web.archive.org/web/20140714214646/http://www.atmel.com/Images/doc2560.pdf |archive-date=2014-07-14 |url-status=live|title=AVR312: Using the USI module as a I<sup>2</sup>C slave|date=2005|publisher=[[Atmel]]|access-date=10 June 2014}}</ref> or UART<ref>{{cite web|url=http://www.atmel.com/Images/doc4300.pdf |archive-url=https://web.archive.org/web/20140714141508/http://www.atmel.com/Images/doc4300.pdf |archive-date=2014-07-14 |url-status=live|title=AVR307: Half Duplex UART Using the USI Module|date=2003|publisher=[[Atmel]]|access-date=10 June 2014}}</ref> interface.
* [[Brownout (electricity)|Brownout]] detection
* [[Watchdog timer]] (WDT)
* Multiple power-saving sleep modes
* Lighting and motor control ([[Pulse-width modulation|PWM]]-specific) controller models
* [[Controller area network|CAN]] controller support
* [[Universal Serial Bus|USB]] controller support
** Proper full-speed (12&nbsp;Mbit/s) hardware & Hub controller with embedded AVR.
** Also freely available low-speed (1.5&nbsp;Mbit/s) ([[Human interface device|HID]]) [[Bit-banging|bitbanging]] software emulations
* [[Ethernet]] controller support
* [[Liquid crystal display|LCD]] controller support
* Low-voltage devices operating down to 1.8&nbsp;V (to 0.7&nbsp;V for parts with built-in DC–DC upconverter)
* picoPower devices
* [[Direct memory access|DMA]] controllers and "event system" peripheral communication.
* Fast cryptography support for [[Advanced Encryption Standard|AES]] and [[Data Encryption Standard|DES]]