Editing Adder (electronics) (section)

==Binary adders==

===Half adder===
The '''half adder''' adds two single binary digits <math>A</math> and <math>B</math>. It has two outputs, sum (<math>S</math>) and carry (<math>C</math>). The carry signal represents an [[Integer overflow|overflow]] into the next digit of a multi-digit addition. The value of the sum is <math>2C + S</math>. The simplest half-adder design, pictured on the right, incorporates an [[XOR gate]] for <math>S</math> and an [[AND gate]] for <math>C</math>. The Boolean logic for the sum (in this case <math>S</math>) will be <math>A \oplus B</math> whereas for the carry (<math>C</math>) will be <math>A \cdot B</math>. With the addition of an [[OR gate]] to combine their carry outputs, two half adders can be combined to make a full adder.<ref name="Lancaster_2004"/>

The [[truth table]] for the half adder is:
:{| class="wikitable" style="text-align:center"
|- 
! colspan="2"| Inputs || colspan="2"| Outputs
|- style="background:#def; text-align:center;"
| '''A''' || '''B''' || '''C'''<sub>out</sub>  || '''S'''
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}}  || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}}  || {{yes2|1}}
|- 
| {{yes2|1}} || {{no2|0}} || {{no2|0}}  || {{yes2|1}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}  || {{no2|0}}
|-
|}

Various half adder digital logic circuits:
<gallery widths="220px" heights="165px">
File:Halfadder.gif|Half adder in action.
File:half Adder.svg|[[Schematic]] of half adder implemented with one [[XOR gate]] and one [[AND gate]].
File:Half adder using NAND gates only.jpg|Schematic of half adder implemented with five [[NAND gate]]s.
File:1-bit half-adder.svg|[[Electronic symbol|Schematic symbol]] for a 1-bit half adder.
</gallery>

===Full adder===
A '''full adder''' adds binary numbers and accounts for values carried in as well as out. A one-bit full-adder adds three one-bit numbers, often written as <math>A</math>, <math>B</math>, and <math>C_{in}</math>; <math>A</math> and <math>B</math> are the operands, and <math>C_{in}</math> is a bit carried in from the previous less-significant stage.<ref name="Mano_1979"/> The circuit produces a two-bit output. Output carry and sum are typically represented by the signals <math>C_{out}</math> and <math>S</math>, where the sum equals <math>2C_{out} + S</math>. The full adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers.

A full adder can be implemented in many different ways such as with a custom [[transistor]]-level circuit or composed of other gates. The most common implementation is with:

:<math>S = A \oplus B \oplus C_{in}</math>
:<math>C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B))</math>

The above expressions for <math>S</math> and <math>C_{in}</math> can be derived from using a [[Karnaugh map]] to simplify the truth table.

In this implementation, the final [[OR gate]] before the carry-out output may be replaced by an [[XOR gate]] without altering the resulting logic. This is because when A and B are both 1, the term <math>(A \oplus B)</math> is always 0, and hence <math>(C_{in} \cdot (A \oplus B))</math> can only be 0. Thus, the inputs to the final OR gate can never be both 1's (this is the only combination for which the OR and XOR outputs differ).

Due to the [[functional completeness]] property of the NAND and NOR gates, a full adder can also be implemented using nine [[NAND gates]],<ref>{{Citation|title=Half Adder and Full Adder Circuits|author-first=Ravi|author-last=Teja|date=2021-04-15|access-date=2021-07-27|url=https://www.electronicshub.org/half-adder-and-full-adder-circuits/#Full_Adder_using_NAND_Gates}}</ref> or nine [[NOR gates]].

Using only two types of gates is convenient if the circuit is being implemented using simple [[integrated circuit]] chips which contain only one gate type per chip.

A full adder can also be constructed from two half adders by connecting <math>A</math> and <math>B</math> to the input of one half adder, then taking its sum-output <math>S</math> as one of the inputs to the second half adder and <math>C_{in}</math> as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output (<math>S</math>) of the full adder and the output from the OR gate is the final carry output (<math>C_{out}</math>). The critical path of a full adder runs through both XOR gates and ends at the sum bit <math>S</math>. Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to:

:<math>T_\text{FA} = 2 \cdot T_\text{XOR} = 2 D</math>

The critical path of a carry runs through one XOR gate in adder and through 2 gates (AND and OR) in carry-block and therefore, if AND or OR gates take 1 delay to complete, has a delay of:

:<math>T_\text{c} = T_\text{XOR} + T_\text{AND} + T_\text{OR} = D + D + D = 3D</math>

The [[truth table]] for the full adder is:
:{| class="wikitable" style="text-align:center"
|- style="background:#def; text-align:center;"
!colspan="3"| Inputs || colspan="2"| Outputs
|- style="background:#def; text-align:center;"
| '''A''' || '''B''' || '''C'''<sub>in</sub> || '''C'''<sub>out</sub>  || '''S'''
|- 
| {{no2|0}} || {{no2|0}} || {{no2|0}}  || {{no2|0}} || {{no2|0}}
|- 
| {{no2|0}} || {{no2|0}} || {{yes2|1}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{no2|0}} || {{yes2|1}} || {{no2|0}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{no2|0}} || {{yes2|1}} || {{yes2|1}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{no2|0}} || {{no2|0}}  || {{no2|0}} || {{yes2|1}}
|- 
| {{yes2|1}} || {{no2|0}} || {{yes2|1}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{no2|0}}  || {{yes2|1}} || {{no2|0}}
|- 
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}}  || {{yes2|1}} || {{yes2|1}}
|-
|}
Inverting all inputs of a full adder also inverts all of its outputs, which can be used in the design of fast ripple-carry adders, because there is no need to invert the carry.<ref name="Fischer"/>

Various full adder digital logic circuits:
<gallery widths="220px" heights="165px">
File:Fulladder.gif|Full adder in action.
File:Full-adder logic diagram.svg|[[Schematic]] of full adder implemented with two [[XOR gate]]s, two [[AND gate]]s, one [[OR gate]].
File:Full Adder using NAND gates.svg|Schematic of full adder implemented with nine [[NAND gate]]s.
File:Full Adder using NOR gates.svg|Schematic of full adder implemented with nine [[NOR gate]]s.
File:Inverting full adder CMOS 24T.svg|Full adder with inverted outputs with single-transistor carry propagation delay in [[CMOS]]<ref name="Fischer"/>
File:1-bit full-adder.svg|[[Electronic symbol|Schematic symbol]] for a 1-bit full adder with ''C''<sub>in</sub> and ''C''<sub>out</sub> drawn on sides of block to emphasize their use in a multi-bit adder
</gallery>

===Adders supporting multiple bits===
====Ripple-carry adder====
[[File:4-bit ripple carry adder.svg|thumb|4-bit adder with logical block diagram shown|alt=4-bit adder with logical block diagram shown]]
[[File:RippleCarry2.gif|thumb|Decimal 4-digit ripple carry adder. FA = full adder, HA = half adder.]]

It is possible to create a logical circuit using multiple full adders to add ''N''-bit numbers. Each full adder inputs a <math>C_{in}</math>, which is the <math>C_{out}</math> of the previous adder. This kind of adder is called a '''ripple-carry adder''' (RCA), since each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder (under the assumption that <math>C_{in} = 0</math>).

The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The [[gate delay]] can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to <math>C_{out}</math> of first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.<ref name="Adder"/>
The general equation for the worst-case delay for a ''n''-bit carry-ripple adder, accounting for both the sum and carry bits, is:

:<math>T_\text{CRA}(n) = T_\text{HA} + (n-1) \cdot T_\text{c} + T_\text{s} = </math><math> T_\text{FA} + (n-1) \cdot T_c = </math><math> 3 D + (n-1) \cdot 2 D = (2n+1) \cdot D</math>

A design with alternating carry polarities and optimized [[AND-OR-Invert]] gates can be about twice as fast.<ref name="Burgess_2011"/><ref name="Fischer">{{Cite web|url=https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|title=Einfache Schaltungsblöcke|accessdate=2021-09-05|archive-url=https://web.archive.org/web/20210905175605/https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|archive-date=2021-09-05|last=Fischer|first=P.|publisher=Universität Heidelberg}}</ref>

====Carry-lookahead adder (Weinberger and Smith, 1958)====

{{main|Carry-lookahead adder}}
[[File:4-bit carry lookahead adder.svg|thumb|4-bit adder with carry lookahead]]
[[File:64-bit lookahead carry unit.svg|thumb|64-bit adder with carry lookahead]]

To reduce the computation time, Weinberger and Smith invented a faster way to add two binary numbers by using [[carry-lookahead adder]]s (CLA).<ref>{{cite journal |first1=A. |last1=Weinberger |first2=J.L. |last2=Smith |title=A Logic for High-Speed Addition |journal=Nat. Bur. Stand. Circ. |issue=591 |pages=3–12 |date=1958 |publisher=National Bureau of Standards |url=https://nvlpubs.nist.gov/nistpubs/Legacy/circ/nbscircular591.pdf}}</ref> They introduced two signals (<math>P</math> and <math>G</math>) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0).  In most cases, <math>P</math> is simply the sum output of a half adder and <math>G</math> is the carry output of the same adder.  After <math>P</math> and <math>G</math> are generated, the carries for every bit position are created.

Mere derivation of Weinberger-Smith CLA recurrence, are: [[Brent–Kung adder]] (BKA),<ref name="Brent-Kung_1982"/> and the [[Kogge–Stone adder]] (KSA).<ref name="Kogge-Stone_1973"/><ref name="ULVD_2015"/>
This was shown in  Oklobdzija and Zeydel paper in IEEE Journal of Solid-State Circuits.<ref>{{cite journal |first1=B.R. |last1=Zeydel |first2=D. |last2=Baran |first3=V.G. |last3=Oklobdzija |title=Energy Efficient Design of High-Performance VLSI Adders |journal=IEEE Journal of Solid-State Circuits |volume=45 |issue=6 |pages=1220–33 |date=June 2010 |doi=10.1109/JSSC.2010.2048730 |url=https://www.acsel-lab.com/Publications/Papers/energy_efficient_adders.pdf}}</ref>

Some other multi-bit adder architectures break the adder into blocks.  It is possible to vary the length of these blocks based on the [[propagation delay]] of the circuits to optimize computation time.  These block based adders include the [[carry-skip adder|carry-skip (or carry-bypass) adder]] which will determine <math>P</math> and <math>G</math> values for each block rather than each bit, and the [[carry-select adder]] which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result ''when'' the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of [[lookahead carry unit]]s.

Other adder designs include the [[carry-select adder]], [[conditional sum adder]], [[carry-skip adder]], and carry-complete adder.

====Carry-save adders====
{{main|Carry-save adder}}

If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.

===3:2 compressors===
A full adder can be viewed as a ''3:2 lossy compressor'': it sums three one-bit inputs and returns the result as a single two-bit number; that is, it maps 8 input values to 4 output values. (the term "compressor" instead of "counter" was introduced in<ref>{{cite journal |first1=V.G. |last1=Oklobdzija |first2=D. |last2=Villeger |title=Improving Multiplier Design By Using Improved Column Compression Tree And Optimized Final Adder In CMOS Technology |journal=IEEE Transactions on VLSI Systems |volume=3 |issue=2 |date=June 1995 |pages=292–301 |doi=10.1109/92.386228 |url=https://www.acsel-lab.com/Publications/Papers/47-multipl-ieee-vlsi-95.pdf }}</ref>)Thus, for example, a binary input of 101 results in an output of {{nobr|1 + 0 + 1 {{=}} 10}} (decimal number 2). The carry-out represents bit one of the result, while the sum represents bit zero.  Likewise, a half adder can be used as a ''2:2 lossy compressor'', compressing four possible inputs into three possible outputs.

Such compressors can be used to speed up the summation of three or more addends.  If the number of addends is exactly three, the layout is known as the [[carry-save adder]].  If the number of addends is four or more, more than one layer of compressors is necessary, and there are various possible designs for the circuit: the most common are [[Dadda tree|Dadda]] and [[Wallace tree]]s.  This kind of circuit is most notably used in [[binary multiplier|multiplier circuits]], which is why these circuits are also known as Dadda and Wallace multipliers.