Editing Addressing mode (section)

==Number of addressing modes==
Computer architectures vary greatly as to the number of addressing modes they provide in hardware. There are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes, even though it requires a few extra instructions, and perhaps an extra register.<ref>{{cite journal|url=http://portal.acm.org/citation.cfm?doid=36204.36193|title=How many addressing modes are enough?|author1=F. Chow|author2=S. Correll|author3=M. Himelstein|author4=E. Killian|author5=L. Weber|journal=ACM SIGARCH Computer Architecture News|year=1987|volume=15|issue=5|pages=117–121|doi=10.1145/36177.36193|url-access=subscription}}</ref><ref>{{cite web|url=http://i.stanford.edu/pub/cstr/reports/csl/tr/86/300/CSL-TR-86-300.pdf|title=An Overview of the MIPS-X-MP Project|author1=John L. Hennessy|author-link1=John L. Hennessy|author2=Mark A. Horowitz|author-link2=Mark Alan Horowitz|year=1986|quote=... MIPS-X uses a single addressing mode: base register plus offset.  This simple addressing mode allows the computation of the effective address to begin very early ...}}</ref>  It has proven<ref>{{cite web|url=http://www.csee.umbc.edu/~squire/cs411_l19.html|title=Lecture 19, Pipelining Data Forwarding|work=CS411 Selected Lecture Notes|author=Dr. Jon Squire}}</ref><ref>{{cite web|url=http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt |title=High Performance Computing, Notes of Class 11 (Sept. 15 and 20, 2000) - Pipelining |access-date=2014-02-08 |url-status=dead |archive-url=https://web.archive.org/web/20131227033204/http://hpc.serc.iisc.ernet.in/~govind/hpc/L10-Pipeline.txt |archive-date=2013-12-27 }}</ref><ref name=Guardian>{{cite book |url=https://books.google.com/books?id=Nibfj2aXwLYC&q=deep%20pipeline%20processor&pg=PA94 |title=Modern Processor Design |author=John Paul Shen, Mikko H. Lipasti |year=2004 |publisher=[[McGraw-Hill Professional]]|isbn=9780070570641 }}</ref> much easier to design [[instruction pipeline|pipelined]] CPUs if the only addressing modes available are simple ones.

Most RISC architectures have only about five simple addressing modes, while CISC architectures such as the DEC VAX have over a dozen addressing modes, some of which are quite complicated. The [[IBM System/360 architecture]] has only four addressing modes; a few more have been added for the [[ESA/390]] architecture.

When there are only a few addressing modes, the particular addressing mode required is usually encoded within the instruction code
(e.g. IBM System/360 and successors, most RISC). But when there are many addressing modes, a specific field is often set aside in the instruction to specify the addressing mode. The DEC VAX allowed multiple memory operands for almost all instructions, and so reserved the first few [[bit]]s of each operand specifier to indicate the addressing mode for that particular operand.
Keeping the addressing mode specifier bits separate from the opcode operation bits produces an [[orthogonal instruction set]].

Even on a computer with many addressing modes, measurements of actual programs<ref name="hennessy-patterson-c54x">{{cite book|url=https://books.google.com/books?id=XX69oNsazH4C&pg=PA104|title=Computer Architecture: A Quantitative Approach|author1=John L. Hennessy|author2=David A. Patterson|author-link2=David Patterson (computer scientist)|page=104|quote=The C54x has 17 data addressing modes, not counting register access, but the four found in MIPS account for 70% of the modes. Autoincrement and autodecrement, found in some RISC architectures, account for another 25% of the usage. This data was collected form a measurement of static instructions for the C-callable library of 54 DSP routines coded in assembly language.|isbn=9780080502526|date=2002-05-29|publisher=Elsevier }}</ref> indicate that the simple addressing modes listed below account for some 90% or more of all addressing modes used. Since most such measurements are based on code generated from high-level languages by compilers, this reflects to some extent the limitations of the compilers being used.<ref>{{cite web|url=http://users.encs.concordia.ca/~tahar/coen6741/notes/Chapter2-4p.pdf|title=Instruction Set Principles: Addressing Mode Usage (Summary)|author=Dr. Sofiène Tahar|quote=3 programs measured on machine with all address modes (VAX) ... 75% displacement and immediate|archive-url=https://web.archive.org/web/20110930125040/http://users.encs.concordia.ca/~tahar/coen6741/notes/Chapter2-4p.pdf|archive-date=2011-09-30 }}</ref><ref name="hennessy-patterson-c54x"/><ref>{{cite book|chapter=Efficient and Language-Independent Mobile Programs|author1=Ali-Reza Adl-Tabatabai|author2=Geoff Langdale|author3=Steven Lucco|author4=Robert Wahbe|title=Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation - PLDI '96|year=1995|pages=127–136|doi=10.1145/231379.231402|isbn=0897917952|s2cid=2534344|quote=79% of all instructions executed could be replaced by RISC instructions or synthesized into RISC instructions using only basic block instruction combination.|chapter-url=http://dl.acm.org/citation.cfm?id=231402}}</ref>