Editing Application-specific integrated circuit (section)

== Standard-cell designs ==
{{Main|Standard cell}}

In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third-party design tools were available, there was not an effective link from the third-party design tools to the [[Integrated circuit layout|layout]] and actual semiconductor process performance characteristics of the various ASIC manufacturers.  Most designers used factory-specific tools to complete the implementation of their designs.  A solution to this problem, which also yielded a much higher density device, was the implementation of [[standard cell]]s.<ref name="MichaelJohnSebastianSmith">{{cite book|author=Smith, Michael John Sebastian|title=Application-Specific Integrated Circuits|publisher=Addison-Wesley Professional|year=1997|isbn=978-0-201-50022-6}}</ref> Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as [[propagation delay]], capacitance and inductance, that could also be represented in third-party tools.  Standard-cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance.  Standard-cell design is intermediate between {{Section link||Gate-array and semi-custom design|nopage=y}} and {{Section link||Full-custom design|nopage=y}} in terms of its non-recurring engineering and recurring component costs as well as performance and speed of development (including [[time to market]]).

By the late 1990s, [[logic synthesis]] tools became available.  Such tools could compile [[Hardware description language|HDL]] descriptions into a gate-level [[netlist]].  Standard-cell [[integrated circuit]]s (ICs) are designed in the following conceptual stages referred to as [[Design flow (EDA)|electronics design flow]], although these stages overlap significantly in practice:
# '''[[Requirements engineering]]''': A team of design engineers starts with a non-formal understanding of the [[Requirement|required functions]] for a new ASIC, usually derived from [[requirements analysis]].
# '''[[Register-transfer level]] (RTL) design''': The design team constructs a description of an ASIC to achieve these goals using a [[hardware description language]].  This process is similar to writing a computer program in a [[High-level programming language|high-level language]].
# '''[[Functional verification]]''': Suitability for purpose is verified by functional verification. This may include such techniques as [[logic simulation]] through [[test bench]]es, [[formal verification]], [[Hardware emulation|emulation]], or creating and evaluating an equivalent pure [[software]] model, as in [[Simics]].  Each verification technique has advantages and disadvantages, and most often several methods are used together for ASIC verification.  Unlike most [[Field-programmable gate array|FPGAs]], ASICs cannot be [[Reconfigurable computing|reprogrammed]] once [[Semiconductor device fabrication|fabricated]] and therefore ASIC designs that are not completely correct are much more costly, increasing the need for full [[test coverage]].
# '''Logic synthesis''': [[Logic synthesis]] transforms the RTL design into a large collection called of lower-level constructs called standard cells.  These constructs are taken from a [[Library (electronics)|standard-cell library]] consisting of pre-characterized collections of [[logic gate]]s performing specific functions.  The standard cells are typically specific to the planned manufacturer of the ASIC.  The resulting collection of standard cells and the needed electrical connections between them is called a gate-level [[netlist]].
# '''Placement''': The gate-level netlist is next processed by a [[placement (EDA)|placement]] tool which places the standard cells onto a region of an [[Die (integrated circuit)|integrated circuit die]] representing the final ASIC.  The placement tool attempts to find an [[Mathematical optimization|optimized]] placement of the standard cells, subject to a variety of specified constraints.
# '''Routing''': An electronics [[Routing (electronic design automation)|routing]] tool takes the physical placement of the standard cells and uses the netlist to create the [[electrical connection]]s between them.  Since the [[Optimization problem#Search space|search space]] is large, this process will produce a "sufficient" rather than "[[Global optimum|globally optimal]]" solution.  The output is a file which can be used to create a set of [[photomask]]s enabling a [[Semiconductor fabrication plant|semiconductor fabrication facility]], commonly called a "fab" or "foundry" to [[Manufacturing|manufacture]] physical [[integrated circuit]]s. Placement and routing are closely interrelated and are collectively called [[place and route]] in electronics design.
# '''Sign-off''': Given the final layout, [[circuit extraction]] computes the [[Parasitic element (electrical networks)|parasitic resistances and capacitances]].  In the case of a [[digital circuit]], this will then be further mapped into [[Propagation delay|delay information]] from which the circuit performance can be estimated, usually by [[static timing analysis]].  This, and other final tests such as [[design rule checking]] and [[power analysis]] collectively called [[Signoff (electronic design automation)|signoff]] are intended to ensure that the device will function correctly over all extremes of the process, voltage and temperature.  When this testing is complete the [[photomask]] information is released for [[chip fabrication]].

These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.<ref>{{Cite book|last=Hurley, Jaden Mclean & Carmen.|title=Logic Design|date=2019|publisher=EDTECH|isbn=978-1-83947-319-7|oclc=1132366891}}</ref>

The design steps also called [[Design flow (EDA)|design flow]], are also common to standard product design. The significant difference is that standard-cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than a full custom design. Standard cells produce a [[Transistor density|design density]] that is cost-effective, and they can also integrate [[Semiconductor intellectual property core|IP cores]] and [[static random-access memory]] (SRAM) effectively, unlike gate arrays.