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Barrel processor
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==Comparison with single-threaded processors== ===Advantages=== A single-tasking processor spends a lot of time idle, not doing anything useful whenever a [[cache miss]] or [[pipeline stall]] occurs. Advantages to employing barrel processors over single-tasking processors include: * The ability to do useful work on the other threads while the stalled thread is waiting. * Designing an ''n''-way barrel processor with an ''n''-deep [[Instruction pipeline|pipeline]] is much simpler than designing a single-tasking processor because a barrel processor never has a [[pipeline stall]] and doesn't need [[Hazard (computer architecture)#Register forwarding|feed-forward]] circuits. * For [[real-time computing|real-time]] applications, a barrel processor can guarantee that a "real-time" thread can execute with precise timing, no matter what happens to the other threads, even if some other thread [[Deadlock (computer science)|locks up]] in an [[infinite loop]] or is [[interrupt storm | continuously interrupted]] by [[hardware interrupt]]s. ===Disadvantages=== There are a few disadvantages to barrel processors. * The state of each thread must be kept on-chip, typically in registers, to avoid costly off-chip context switches. This requires a large number of registers compared to typical processors. * Either all threads must share the same [[CPU cache|cache]], which slows overall system performance, or there must be one unit of cache for each execution thread, which can significantly increase the [[transistor count]] and thus the cost of such a CPU. However, in [[Real-time computing#Criteria for real-time computing|hard real-time]] [[embedded system]]s where barrel processors are often found, memory access costs are typically calculated assuming worst-case cache behavior, so this is a minor concern.{{cn|reason="Minor concern" seems to be too all-encompassing unless this is genuinely the case for all barrel processors|date=January 2020}} Some barrel processors such as the [[XMOS]] XS1 do not have a cache at all.
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