Editing Berkeley RISC (section)

==RISC I==

[[File:RISC-I Gold die shot.jpg|thumb|RISC I die shot. Most of the chip is occupied by the register file (bottom left area). Control logic only occupies the small top right corner.]]
The first attempt to implement the RISC concept was originally named ''Gold''. Work on the design started in 1980 as part of a VLSI design course, but the then-complicated design crashed almost all existing design tools. The team had to spend considerable amounts of time improving or re-writing the tools, and even with these new tools it took just under an hour to extract the design on a [[VAX-11/780]].

The final design, named ''RISC I'', was published in [[Association for Computing Machinery]] (ACM) [[International Symposium on Computer Architecture]] (ISCA) in 1981. It had 44,500 transistors implementing 31 instructions and a register file containing 78 32-bit registers. This allowed for six register windows containing 14 registers. Of those 14 registers, 4 were overlapped from the prior window.
The total is then: 10*6 registers in windows + 18 globals=78 registers total. The control and instruction decode section occupied only 6% of the die, whereas the typical design of the era used about 50% for the same role. The register file took up most of that space.<ref name="Peck 83">{{cite tech report |url=http://www.eecs.berkeley.edu/Pubs/TechRpts/1983/CSD-83-135.pdf |title=The VLSI Circuitry of RISC I |id=CSD-83-135 |last=Peek |first=James B. |date=1983-06-02 |publisher=University of California at Berkeley |location=Berkeley, CA, US |pages=13, 59}}</ref>

RISC I also featured a two-stage [[instruction pipeline]] for additional speed, but without the complex instruction re-ordering of more modern designs. This makes conditional branches a problem, because the compiler has to fill the instruction following a conditional branch (the so-called ''[[branch delay slot]]''), with something selected to be "safe" (i.e., not dependent on the outcome of the conditional). Sometimes the only suitable instruction in this case is <code>[[NOP (code)|NOP]]</code>. A notable number of later RISC-style designs still require the consideration of branch delay.

After a month of validation and debugging, the design was sent to the innovative [[MOSIS]] service for production on June 22, 1981, using a 2 μm (2,000&nbsp;nm) process. A variety of delays forced them to abandon their masks four separate times, and wafers with working examples did not arrive back at Berkeley until May 1982. The first working RISC I "computer" (actually a checkout board) ran on June 11. In testing, the chips proved to have lesser performance than expected. In general, an instruction would take 2 μs to complete, while the original design allotted for about .4 μs (five times as fast). The precise reasons for this problem were never fully explained. However, throughout testing it was clear that certain instructions did run at the expected speed, suggesting the problem was physical, not logical.

Had the design worked at full speed, performance would have been excellent. Simulations using a variety of small programs compared the 4&nbsp;MHz RISC I to the 5&nbsp;MHz [[32-bit]] [[VAX|VAX 11/780]] and the 5&nbsp;MHz [[16-bit]] [[Zilog Z8000]] showed this clearly. Program size was about 30% larger than the VAX but very close to that of the Z8000, validating the argument that the higher [[code density]] of CISC designs was not actually all that impressive in reality. In terms of overall performance, the simulations indicated that a full-speed RISC I would have been twice as fast as the VAX, and about four times that of the Z8000. The programs ended up performing about the same overall number of memory accesses because the large register file dramatically improved the odds the needed operand was already on-chip.

It is important to put this performance in context. Even though the RISC I hardware had run slower than the VAX, it made no difference to the importance of the design. RISC allowed for the production of a true 32-bit processor on a real chip die using what was already an older fab. Traditional designs simply could not do this; with so much of the chip surface dedicated to decoder logic, a true 32-bit design like the [[Motorola 68020]] required newer fabs before becoming practical. Using the same fabs, RISC I could have largely outperformed the competition.

On February 12, 2015, IEEE installed a plaque at UC Berkeley to commemorate the contribution of RISC-I.<ref>{{Cite web|url=https://risc.berkeley.edu/risc-i/reunion/memorabilia|title=memorabilia [RISC-I Reunion]|website=risc.berkeley.edu|access-date=2020-03-19}}</ref> The plaque reads:
* ''UC Berkeley students designed and built the first VLSI reduced instruction set computer in 1981. The simplified instructions of RISC-I reduced the hardware for instruction decode and control, which enabled a flat 32-bit address space, a large set of registers, and pipelined execution. A good match to C programs and the Unix operating system, RISC-I influenced instruction sets widely used today, including those for game consoles, smartphones and tablets.''