Editing Branch predictor (section)

===Static branch prediction===
Static prediction is the simplest branch prediction technique because it does not rely on information about the dynamic history of code executing. Instead, it predicts the outcome of a branch based solely on the branch instruction.<ref>{{cite book |author-last1=Shen |author-first1=John P. |author-last2=Lipasti |author-first2=Mikko |title=Modern processor design: fundamentals of superscalar processors |url=https://archive.org/details/modernprocessord00shen |url-access=limited |date=2005 |publisher=[[McGraw-Hill Higher Education]] |location=Boston |isbn=0-07-057064-7 |pages=[https://archive.org/details/modernprocessord00shen/page/n236 455]}}</ref>

The early implementations of [[SPARC]] and [[MIPS architecture|MIPS]] (two of the first commercial [[RISC]] architectures) used single-direction static branch prediction: they always predict that a conditional jump will not be taken, so they always fetch the next sequential instruction. Only when the branch or jump is evaluated and found to be taken, does the instruction pointer get set to a non-sequential address.

Both CPUs evaluate branches in the decode stage and have a single cycle instruction fetch. As a result, the branch target recurrence is two cycles long, and the machine always fetches the instruction immediately after any taken branch. Both architectures define [[branch delay slot]]s in order to utilize these fetched instructions.

A more advanced form of static prediction presumes that backward branches will be taken and that forward branches will not. A backward branch is one that has a target address that is lower than its own address. This technique can help with prediction accuracy of loops, which are usually backward-pointing branches, and are taken more often than not taken.

Some processors allow branch prediction hints to be inserted into the code to tell whether the static prediction should be taken or not taken. The Intel [[Pentium 4]] accepts branch prediction hints, but this feature was abandoned in later Intel processors.<ref name="Fog_Microarchitecture">{{cite web |author-last=Fog |author-first=Agner |title=The microarchitecture of Intel, AMD, and VIA CPUs |date=2016-12-01 |url=http://www.agner.org/optimize/microarchitecture.pdf |page=36 |access-date=2017-03-22}}</ref>

Static prediction is used as a fall-back technique in some processors with dynamic branch prediction when dynamic predictors do not have sufficient information to use. Both the Motorola [[PowerPC G4#PowerPC 7450 .22Voyager.22|MPC7450 (G4e)]] and the Intel [[Pentium 4]] use this technique as a fall-back.<ref>{{cite web|url=https://arstechnica.com/articles/paedia/cpu/p4andg4e.ars/4|title=The Pentium 4 and the G4e: an Architectural Comparison|website=[[Ars Technica]]|date=12 May 2001 }}</ref>

In static prediction, all decisions are made at compile time, before the execution of the program.<ref>{{cite web |url=http://ece-research.unm.edu/jimp/611/slides/chap4_5.html |title=CMSC 611: Advanced Computer Architecture, Chapter 4 (Part V) |author-first=Jim |author-last=Plusquellic}}</ref>