Editing CDC Cyber (section)

===Cyber 70 and 170 series===
[[Image:CDC Cyber 170 CPU architecture.png|thumb|300px|right|Hardware architecture of the CDC Cyber 170 series computer]]
[[Image:Modul CDC Cyber 175.jpg|thumb|225px|Module of the CDC Cyber 175 operated at [[RWTH Aachen University]], about 1985]]

The Cyber 70 and 170 architectures were successors to the earlier [[CDC 6600]] and [[CDC 7600]] series and therefore shared almost all of the earlier architecture's characteristics.  The Cyber-70 series is a minor upgrade from the earlier systems.  The Cyber-73 was largely the same hardware as the CDC 6400 - with the addition of a Compare and Move Unit (CMU).  The CMU instructions speeded up comparison and moving of non-word aligned 6-bit character data.  The Cyber-73 could be configured with either one or two CPUs.  The dual CPU version replaced the CDC 6500.  As was the case with the CDC 6200, CDC also offered a Cyber-72.  The Cyber-72 had identical hardware to a Cyber-73, but added additional clock cycles to each instruction to slow it down.  This allowed CDC to offer a lower performance version at a lower price point without the need to develop new hardware.  It could also be delivered with dual CPUs.  The Cyber 74 was an updated version of the CDC 6600.<ref>[https://www.museumwaalsdorp.nl/en/history/comphistory/computer-history-the-period-1978-1983/comp781e/ Museum Waalsdorp]</ref>  The Cyber 76 was essentially a renamed [[CDC 7600]].  Neither the Cyber-74 nor the Cyber-76 had CMU instructions.

The Cyber-170 series represented CDCs move from discrete [[electronic component]]s and [[magnetic-core memory|core memory]] to [[integrated circuit]]s and [[semiconductor memory]].  The 172, 173, and 174 use integrated circuits and semiconductor memory whereas the 175 uses high-speed discrete transistors.<ref>[[Computerworld]], November 19, 1975, p. 47</ref>  The Cyber-170/700 series is a late-1970s refresh of the Cyber-170 line.

The central [[Central processing unit|processor]] (CPU) and central memory (CM) operated in units of 60-bit [[Word (data type)|words]].  In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors).  Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits.
The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which is [[semiconductor]] memory in this series.  The central processor has no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.

A Cyber 170-series system consists of one or two [[Central processing unit|CPUs]] that run at either 25 or 40&nbsp;MHz, and is equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed [[I/O]]. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating-point divides), the higher-end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) are equipped with eight or twelve words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which is usually called ''in-stack'') runs very fast, without referencing main memory for instruction fetch.  The lower-end models do not contain an instruction stack.  However, since up to four instructions are packed into each 60-bit word, some degree of prefetching is inherent in the design.

As with predecessor systems, the Cyber 170 series has eight 18-bit address [[Processor register|registers]] (A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7).  Seven of the A registers are tied to their corresponding X register.  Setting A1 through A5 reads that address and fetches it into the corresponding X1 through X5 register.  Likewise, setting register A6 or A7 writes the corresponding X6 or X7 register to central memory at the address written to the A register.  A0 is effectively a scratch register.

The higher-end CPUs consisted of multiple [[Execution unit|functional units]] (e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions.  This parallelism allows assembly programmers to minimize the effects of the system's slow memory fetch time by ''pre-fetching'' data from central memory well before that data is needed.  By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch can be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer can write extremely efficient code that makes the most of the power of the hardware.

The peripheral processor subsystem uses a technique known as ''barrel and slot'' to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware [[multiprogramming]]. The peripheral processors have 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP has access to all [[I/O]] channels and all of the system's central memory (CM) in addition to the PP's own memory.  The PP instruction set lacks, for example, extensive arithmetic capabilities and does not run user code; the peripheral processor subsystem's purpose is to process I/O and thereby free the more powerful central processor unit(s) to running user computations.

[[File:CDC 22-ring binder.JPG|thumb|CDC documentation came in single sheets punched for three-ring- or twenty-two-ring binders, so updates were easily accomplished.]]

A feature of the lower Cyber CPUs is the Compare Move Unit (CMU).  It provides four additional instructions intended to aid text processing applications.  In an unusual departure from the rest of the 15- and 30-bit instructions, these are 60-bit instructions (three actually use all 60 bits, the other use 30 bits, but its alignment requires 60 bits to be used).  The instructions are: move a short string, move a long string, compare strings, and compare a collated string.  They operate on six-bit fields (numbered 1 through 10) in central memory.  For example, a single instruction can specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9".  The CMU hardware is not included in the higher-end Cyber CPUs, because [[Hand coding|hand coded]] loops could run as fast or faster than the CMU instructions.

Later systems typically run CDC's [[NOS (operating system)|NOS]] (Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982, with the final version of 2.8.7 PSR 871, delivered in December 1997, which continues to have minor unofficial bug fixes, Y2K mitigation, etc in support of DtCyber.  Besides NOS, the only other operating systems commonly used on the 170 series was ''[[NOS/BE]]'' or its predecessor ''[[CDC SCOPE|SCOPE]]'', a product of CDC's Sunnyvale division.  These operating systems provide [[time-sharing]] of batch and interactive applications.  The predecessor to NOS was ''[[CDC Kronos|Kronos]]'' which was in common use up until 1975 or so.  Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems rather than convert their applications.  Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility.