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== Desktop Celerons == === P6-based Celerons === {{Main|List of Intel Celeron microprocessors#P6 based Celerons}} ==== {{Anchor|Covington}}Covington ==== [[Image:KL Intel Celeron Covington.jpg|right|thumb|180px|Intel Celeron Covington]] Launched in April 1998, the first ''Covington'' Celeron was essentially a 266 MHz Pentium II manufactured without any secondary cache at all.<ref>{{cite magazine |last=Slater |first=Michael |title=Microprocessors have PCs humming |url=http://www.eetimes.com/myf98/ao_slater.html |magazine=[[EE Times]] |date=May 27, 1998 |access-date=July 30, 2007}}</ref> Covington also shared the 80523 product code of Deschutes. Although clocked at 266 or 300 MHz (frequencies 33 or 66 MHz higher than the desktop version of the Pentium w/MMX), the cacheless Celerons had trouble outcompeting the parts they were designed to replace.<ref name="S7toS1" /> Substantial numbers were sold on first release, largely on the strength of the Intel name, but the Celeron quickly achieved a poor reputation both in the trade press and among computer professionals.<ref>{{cite web |last=Zisman |first=Alex |title=Say No to Celeron |url=http://www.zisman.ca/Articles/1998/Celeron.html |work=Canadian Computer Wholesaler |date=June 1998 |access-date=July 30, 2007}}</ref> The initial market interest faded rapidly in the face of its poor performance, and with sales at a very low level, Intel felt obliged to develop a substantially faster replacement as soon as possible. Nevertheless, the first Celerons were quite popular among some overclockers, for their flexible [[overclocking|overclockability]] and reasonable price.<ref name="S7toS1" /> Covington was only manufactured in [[Slot 1]] SEPP format. ==== {{Anchor|Mendocino}}Mendocino ==== {{redirect|Mendocino (microprocessor)|the AMD mobile APU|List of AMD mobile processors#Mendocino (7020 series, Zen2/RDNA2 based)}} [[Image:Intel Celeron 300A MHz.jpg|thumb|180px|right|Intel Celeron Mendocino 300 MHz in SEPP package]] [[Image:KL Intel Celeron Mendocino Top.jpg|thumb|150px|right|Top of a Mendocino-core Socket 370 Celeron (PPGA package)]] [[Image:KL Intel Celeron Mendocino S370.jpg|thumb|150px|right|Underside of a Mendocino-core Socket 370 Celeron, 333 MHz]] [[File:Intel Celeron 500MHz Mendocino SL3LQ (PNG).png|thumb|Intel Celeron 500MHz Mendocino die shot]] The ''Mendocino'' Celeron, launched August 24, 1998, was the first retail CPU to use on-die [[L2 cache]]. Whereas Covington had no secondary cache at all, Mendocino included 128 KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300 MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300 MHz, Intel called the Mendocino core Celeron ''300A''.<ref name="BigCPUShootout">{{cite news|last=Pabst|first=Thomas|title=Big CPU Shoot Out: Intel Launches New Celeron with Mendocino Core and Pentium II 450|url=http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|archive-url=https://archive.today/20130204153422/http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|url-status=dead|archive-date=February 4, 2013|publisher=[[Tom's Hardware Guide]]|date=August 24, 1998|access-date=July 30, 2007}}</ref> Although the other Mendocino Celerons (the 333 MHz part, for example) did not have an ''A'' appended, some people call all Mendocino processors ''Celeron-A'' regardless of clock rate. The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as ''too'' successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. [[Overclocking|Overclockers]] soon discovered that, given a high-end [[motherboard]], many Celeron 300A CPUs could run reliably at 450 MHz. This was achieved by simply increasing the [[front-side bus]] (FSB) clock rate from the stock 66 MHz to the 100 MHz clock of the [[Pentium II]], helped by several facts: the 440BX chipset with nominal support for 100 MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available.<ref name="BigCPUShootout" /> Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66 MHz. However, [[overclocking|overclockers]] soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100 MHz bus.<ref>{{cite web|url=http://www.tomshardware.com/reviews/66-mhz-slot-1-cpus-running-100-mhz,66.html|title=How to Get All 66 MHz Slot 1 CPUs Running 100 MHz|author=Thomas Pabst|work=Tom's Hardware|date=May 14, 1998 }}</ref> At the time on-die cache was difficult to manufacture; especially [[L2 cache|L2]] as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary [[L2 cache]], which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512 KB or 1 MB), but they carried the performance penalty of slower cache performance, typically running at a [[Front-side bus|FSB]] frequency of 60 to 100 MHz. The Pentium II's 512 KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special [[back-side bus]]. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.<ref>{{cite news|last=Joch |first=Alan |title=Buses: Front-side and backside |url=http://www.itworld.com/Comp/1091/CWD010430STO60015/ |publisher=ITworld.com |date=April 30, 2001 |access-date=July 30, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archive-date=May 2, 2001 |df=dmy }}</ref> Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533 MHz. The Mendocino Celeron CPU came only designed for a 66 MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels. The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and [[Socket 370]] [[Pin grid array#Plastic|PPGA]] package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466 MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed [[Slotket]]s) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported [[symmetric multiprocessing]] (SMP), and there was at least one motherboard released (the [[ABIT BP6]]) which took advantage of this fact. The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466 MHz. In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related ''Dixon'' Mobile Pentium II variant. ==== Coppermine-128 ==== {{multiple image | total_width = 320 | image1 = Celeron Coppermine-128 600.jpg | caption1 = Celeron ''Coppermine 128'' 600 MHz ([[FC-PGA]] package) | image2 = Celeron Coppermine-128 600 back.jpg | caption2 = Underside of a Celeron ''Coppermine 128'', 600 MHz }} The next generation Celeron was the '' '[[Coppermine (microprocessor)|Coppermine]]-128' '' (sometimes known as the ''Celeron II''). These were a derivative of Intel's ''Coppermine'' [[Pentium III]] and were released on March 29, 2000.<ref>{{cite news |last=Hachman |first=Mark |title=Intel launches Celerons with SIMD instruction-set extensions |url=http://www.my-esm.com/digest/story/OEG20000329S0006 |publisher=My-ESM |date=March 29, 2000 |access-date=July 31, 2007 |archive-url=https://web.archive.org/web/20070927070052/http://www.my-esm.com/digest/story/OEG20000329S0006 |archive-date=September 27, 2007 |url-status=dead |df=dmy }}</ref> This Celeron used a Coppermine core with half of its L2 cache switched off, resulting in 128 KB of 4-way associative on-chip L2 cache as on the Mendocino, and was initially likewise restricted to a 66 MHz Front Side Bus speed. Despite the halved associativity on the L2 cache, which reduced hit rates compared to the full Coppermine design, it kept the 256-bit wide L2 cache bus, which meant an advantage compared to Mendocino and older Katmai/Pentium II designs, which all had a 64-bit datapath to their L2 caches.<ref>{{cite web|url=https://www.anandtech.com/show/519/5|title=Intel Celeron 600 "Coppermine128"|first=Anand Lal|last=Shimpi|website=anandtech.com|access-date=April 4, 2018}}</ref><ref>{{cite web|url=https://www.anandtech.com/show/568/2|title=Intel Celeron 700|first=Anand Lal|last=Shimpi|website=anandtech.com|access-date=April 4, 2018}}</ref> [[Streaming SIMD Extensions|SSE]] instructions were also enabled. All Coppermine-128s were produced in the same [[FCPGA]] Socket 370 format that most Coppermine Pentium III CPUs used. These Celeron processors began at 533 MHz and continued through 566, 600, 633, 667, 700, 733, and 766 MHz. Because of the limitations of the 66 MHz bus, there were diminishing returns on performance as clock rates increased. On January 3, 2001, Intel switched to a 100 MHz bus with the launch of the 800 MHz Celeron, resulting in a significant performance-per-clock improvement.<ref>{{cite news|last=Lal Shimpi| first=Anand| author-link=Anand Lal Shimpi | title=Intel Celeron 800: The first 100 MHz FSB Celeron | url=http://www.anandtech.com/showdoc.aspx?i=1393&p=1 | publisher=[[AnandTech]]|date=January 3, 2001|access-date=July 30, 2007}}</ref> All Coppermine-128 CPUs from 800 MHz and higher use the 100 MHz front side bus. Various models were made at 800, 850, 900, 950, 1000, and 1100 MHz. In Intel's "Family/Model/Stepping" scheme, Coppermine Celerons and Pentium IIIs are family 6, model 8 and their Intel product code is 80526. ==== Tualatin-256 ==== [[Image:Tualeron 1200.jpg|thumb|150px|A Tualatin-core Celeron 1.2 GHz (''Tualeron'') (FC-PGA2 package)]] These Celeron processors, released initially at 1.2 GHz on October 2, 2001,<ref>{{cite news|last=Sigvartsen |first=Ana |title=Intel's Celeron reaches 1.2 GHz |url=http://www.infosatellite.com/news/2001/10/j031001celeron_12ghz.html |publisher=Infosatellite.com |date=October 2, 2001 |access-date=July 31, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20071012160212/http://infosatellite.com/news/2001/10/j031001celeron_12ghz.html |archive-date=October 12, 2007 }}</ref> were based on the Pentium III ''' '[[Pentium III#Tualatin|Tualatin]]'''' core and made with a 0.13 micrometer process for the [[FCPGA|FCPGA 2]] Socket 370. They were nicknamed "Tualeron" by some enthusiasts — a portmanteau of the words [[Pentium III#Tualatin|Tualatin]] and Celeron. Some software and users refer to the chips as ''Celeron-S'', referring to the chip's lineage with the Pentium III-S, but this is not an official designation. Intel later released 1 GHz and 1.1 GHz parts (which were given the extension ''A'' to their name to differentiate them from the Coppermine-128 of the same clock rate they replaced).<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel's Celeron gets major power boost|url=http://www.infosatellite.com/news/2001/12/h071201celeron_tualatin.html|publisher=Infosatellite.com|date=December 7, 2001|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160217/http://infosatellite.com/news/2001/12/h071201celeron_tualatin.html|archive-date=October 12, 2007|df=dmy-all}}</ref> A 1.3 GHz chip, launched January 4, 2002,<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel launches Celeron 1.3 GHz|url=http://www.infosatellite.com/news/2002/01/h040102intel_celeron_3ghz.html|publisher=Infosatellite.com|date=January 4, 2002|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160232/http://infosatellite.com/news/2002/01/h040102intel_celeron_3ghz.html|archive-date=October 12, 2007|df=dmy-all}}</ref> and finally a 1.4 GHz chip, launched May 15, 2002 (the same day as the 1.7 GHz Willamette-based Celeron launch),<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel launches Celeron with new core|url=http://www.infosatellite.com/news/2002/05/a160502celerons.html|publisher=Infosatellite.com|date=May 16, 2002|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160237/http://infosatellite.com/news/2002/05/a160502celerons.html|archive-date=October 12, 2007|df=dmy-all}}</ref> marked the end of the Tualatin-256 line. The most significant differences compared to the Pentium III Tualatin are a lower 100 MHz bus and fixed 256 KB of L2 cache (whereas the Pentium III was offered with either 256 KB or 512 KB L2 cache); cache associativity stayed at 8-way,<ref>download.intel.com/support/processors/celeron/sb/29859604.pdf</ref> although the newly introduced data prefetching appears to have been disabled.<ref>{{cite web|url=https://www.realworldtech.com/data-prefetching/|title=Data Prefetch Logic - What is it Worth?|website=www.realworldtech.com|access-date=April 4, 2018}}</ref> Furthermore, the Tualatin-256's L2 cache has a higher latency which boosted manufacturing yields for this budget CPU.{{Citation needed|date=December 2017}} On the other hand, this improved stability when overclocking and most of them had no problem working at 133 MHz FSB for a substantial performance increase. Despite offering much improved performance over the Coppermine Celeron it superseded, the Tualatin Celeron still suffered stiff competition from AMD's [[Duron]] budget processor.<ref>{{cite news|first=Frank| last=Völkel |author2=Töpelt, Bert|title=Intel vs. AMD: Celeron 1300 vs. Duron 1200|url=http://www.tomshardware.com/2002/01/03/intel_vs/|publisher=[[Tom's Hardware Guide]] | date=January 3, 2002|access-date=July 31, 2007}}</ref> Intel later responded by releasing the NetBurst Willamette Celeron, and for some time Tualatin Celerons were manufactured and sold in parallel with the Pentium 4-based Celerons that replaced them. In Intel's "Family/Model/Stepping" scheme, Tualatin Celerons and Pentium IIIs are family 6, model 11 and their Intel product code is 80530. === NetBurst-based Celerons === {{Main|List of Intel Celeron microprocessors#Netburst based Celerons}} ==== Willamette-128 ==== These Celerons were for socket 478 and were based on the ''[[Pentium 4#Willamette|Willamette]]'' [[Pentium 4]] core, being a completely different design compared to the previous Tualatin Celeron. These are often known as the ''Celeron 4''. Their L2 cache (128 KB) is half that of the ''Willamette''-based Pentium 4's 256 KB of L2 cache, but otherwise the two are very similar. With the transition to the Pentium 4 core the Celeron now featured SSE2 instructions. The ability to share the same socket as the Pentium 4 meant that the Celeron now had the option to use [[RDRAM]], [[DDR SDRAM]], or traditional [[SDRAM#SDR SDRAM|SDRAM]]. Willamette Celerons were launched May 15, 2002, initially at 1.7 GHz, and offered a noticeable performance improvement over the older 1.3 GHz ''Tualatin''-based Celeron part, being able to finally outperform a 1.3 GHz AMD Duron, which at the time was AMD's top competing budget processor.<ref>{{cite news|last=Schmidt|first=Patrick|title=Good Old Newbie: Intel's 1.7 GHz Celeron for Socket 478|url=http://www.tomshardware.com/2002/05/15/good_old_newbie/|archive-url=https://web.archive.org/web/20071213032908/http://www.tomshardware.com/2002/05/15/good_old_newbie/|url-status=dead|archive-date=December 13, 2007|publisher=[[Tom's Hardware Guide]]|date=May 15, 2002|access-date=July 30, 2007}}</ref> On June 12, 2002, Intel launched the last Willamette Celeron, a 1.8 GHz model.<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel pushes Celerons to 1.8 GHz|url=http://www.infosatellite.com/news/2002/06/a130602celeron_18.html|publisher=Infosatellite.com|date=June 13, 2002|access-date=July 30, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160258/http://infosatellite.com/news/2002/06/a130602celeron_18.html|archive-date=October 12, 2007|df=dmy-all}}</ref> It contains 42 million transistors and has a die area of 217 mm<sup>2</sup>.<ref>{{cite web|url=http://www.chiplist.com/Intel_Pentium_4_Celeron_processor_Willamette_128/tree3f-subsection--2027-/|title=Intel Pentium 4 Celeron processor (Willamette-128)|work=chiplist.com}}</ref> In Intel's "Family/Model/Stepping" scheme, Willamette Celerons and Pentium 4s are family 15, model 1, and their Intel product code is 80531. ==== Northwood-128 ==== These socket 478 Celerons are based on the ''[[Pentium 4#Northwood|Northwood]]'' Pentium 4 core, and also have 128 KB of L2 cache. The only difference between the ''Northwood-128''-based and the ''Willamette-128''-based Celeron is the fact that it was built on the new 130 nm process which shrank the die size, increased the transistor count, and lowered the core voltage from 1.7 V on the ''Willamette-128'' to 1.52 V for the ''Northwood-128''. Despite these differences, they are functionally the same as the Willamette-128 Celeron, and perform largely the same clock-for-clock. The ''Northwood-128'' family of processors were initially released as a 2 GHz core (a 1.9 GHz model was announced earlier, but never launched<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel plans faster 0.13-micron Celeron|url=http://www.infosatellite.com/news/2002/06/a170602celeron.html|publisher=Infosatellite.com|date=June 17, 2002|access-date=July 30, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071012160303/http://infosatellite.com/news/2002/06/a170602celeron.html|archive-date=October 12, 2007|df=dmy-all}}</ref>) on September 18, 2002.<ref>{{cite news|last=Sigvartsen|first=Ana|title=Intel launches new Celeron, updates prices|url=http://www.infosatellite.com/news/2002/09/a190902celeron.html|publisher=Infosatellite.com|date=September 19, 2002|access-date=July 30, 2007|url-status=dead|archive-url=https://web.archive.org/web/20071006095201/http://www.infosatellite.com/news/2002/09/a190902celeron.html|archive-date=October 6, 2007|df=dmy-all}}</ref> Since that time Intel has released a total of 10 different clock speeds ranging from 1.8 GHz to 2.8 GHz, before being surpassed by the Celeron D. Although the ''Northwood''-based Celerons suffer considerably from their small L2 cache, some clock rates have been favored in the enthusiast market because, like the old 300A, they can run well above their specified clock rate.<ref name="Schmid" /> In Intel's "Family/Model/Stepping" scheme, Northwood Celerons and Pentium 4s are family 15, model 2, and their Intel product code is 80532. ==== Prescott-256 {{Anchor|Celeron D}} ==== [[File:Intel Celeron D 340 (Prescott) (JPG).jpg|thumb|Prescott Celeron D 340 die shot ]] Prescott-256 '''Celeron D''' processors, initially launched June 25, 2004,<ref>{{cite news|last=Shilov|first=Anton|title=Intel Officially Launched Celeron D Processors.|url=http://www.xbitlabs.com/news/cpu/display/20040625022821.html|publisher=X-bit labs|date=June 25, 2004|access-date=July 31, 2007|url-status=dead|archive-url=https://web.archive.org/web/20070930014514/http://www.xbitlabs.com/news/cpu/display/20040625022821.html|archive-date=September 30, 2007|df=dmy-all}}</ref> featuring double the L1 cache (16 KB) and L2 cache (256 KB) as compared to the previous Willamette and Northwood desktop Celerons, by virtue of being based on the ''[[Pentium 4#Prescott|Prescott]]'' Pentium 4 core.<ref>{{cite news|last=Wilson|first=Derek|title=Intel Celeron D: New, Improved & Exceeds Expectations|url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2093| publisher=[[AnandTech]]|date=June 24, 2004|access-date=July 31, 2007}}</ref> It also features a 533 MT/s bus and [[SSE3]], and a 3xx model number (compared to 5xx for Pentium 4s and 7xx for Pentium Ms). The Prescott-256 Celeron D was manufactured for [[Socket 478]] and [[LGA 775]], with 3x0 and 3x5 designations from 310 through to 355 at clock speeds of 2.13 GHz to 3.33 GHz. The Intel Celeron D processor works with the Intel 845 and 865 chipset families. The ''D'' suffix actually has no official designation and does not indicate that these models are dual-core. It is used simply to distinguish this line of Celeron from the previous, lower performing Northwood and Willamette series, and also from the mobile series, the Celeron M (which also uses 3xx model numbers).<ref>{{cite news|last=Aubrey|first=John|title=Celeron D: the Little Processor that Could|url=http://www.devhardware.com/c/a/Computer-Processors/Celeron-D-the-Little-Processor-that-Could|publisher=Dev Hardware| date=April 18, 2005| access-date=September 23, 2006}}</ref> Unlike the [[Pentium D]], the Celeron D is ''not'' a dual core processor. The Celeron D was a major performance improvement over previous NetBurst-based Celerons. A test using a variety of applications, run by Derek Wilson at Anandtech.com, showed that the new Celeron D architecture alone offered up performance improvements on average of >10% over a Northwood Celeron when both CPUs were run at the same bus and clock rate.<ref>{{cite news|last=Wilson|first=Derek|title=Intel Celeron D: New, Improved & Exceeds Expectations|url=http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2093&p=5|publisher=[[AnandTech]]| date=June 24, 2004|access-date=July 31, 2007}}</ref> This CPU also had the addition of SSE3 instructions and the higher FSB which only contributed to this already impressive gain. Despite its many improvements, the ''Prescott'' core of the Celeron D had at least one major drawback{{snd}} heat. Unlike the fairly cool-running Northwood Celeron, the Prescott-256 had a class-rated [[thermal design power|TDP]] of 73 W, which prompted Intel to include a more intricate copper core/aluminum finned cooler to help handle the additional heat.<ref>{{cite news | last=Gavrichenkov | first=Ilya | title=Intel Celeron D CPU: Budget Processors from Intel Acquire Prescott Core | url=http://www.xbitlabs.com/articles/cpu/display/celeron-d_6.html | publisher=X-bit labs | date=June 25, 2004 | access-date=July 31, 2007 | url-status=dead | archive-url=https://web.archive.org/web/20070807042345/http://www.xbitlabs.com/articles/cpu/display/celeron-d_6.html | archive-date=August 7, 2007 | df=dmy-all }}</ref> In mid-2005, Intel refreshed the Celeron D with [[Intel 64]] and [[XD Bit]] (eXecute Disable) enabled. Model numbers increase by 1 over the previous generation (e.g., 330 became 331). This only applied to [[LGA 775]] Celeron Ds. There are no [[Socket 478]] CPUs with XD Bit capabilities. In Intel's "Family/Model/Stepping" scheme, Prescott Celeron Ds and Pentium 4s are family 15, model 3 (up to stepping E0) or 4 (stepping E0 onwards), and their Intel product code is 80546 or 80547, depending on socket type. ==== Cedar Mill-512 ==== Based on the ''Cedar Mill'' Pentium 4 core, this version of the Celeron D was launched May 28, 2006, and continued the 3xx naming scheme with the Celeron D 347 (3.06 GHz), 352 (3.2 GHz), 356 (3.33 GHz), 360 (3.46 GHz), and 365 (3.6 GHz). The Cedar Mill Celeron D is largely the same as the Prescott-256, except with double the L2 cache (512 KB) and based on a 65 nm manufacturing process. The Cedar Mill-512 Celeron D is LGA 775 exclusive. The main benefits of the Cedar Mill Celerons over the Prescott Celerons are the slightly increased performance due to the larger L2 cache, higher clock rates, and less heat dissipation, with several models having a TDP lowered to 65 W from Prescott's lowest offering of 73 W.<ref>{{cite news|last=Kowaliski|first=Cyril|title=65 nm Celeron Ds coming May 28|url=http://techreport.com/onearticle.x/9982|publisher=[[The Tech Report]]|date=May 16, 2006|access-date=July 31, 2007}}</ref> In Intel's "Family/Model/Stepping" scheme, Cedar Mill Celeron Ds and Pentium 4s are family 15, model 6, and their Intel product code is 80552. === Core-based Celerons === {{Main|List of Intel Celeron microprocessors#Core based Celerons}} ==== Conroe-L ==== [[Image:Intel Celeron 420.png|thumb|150px|Celeron 420 (Conroe-L, 1.6 GHz)]] {{Main|Conroe (microprocessor)#Conroe-L}} The Conroe-L Celeron is a single-core processor built on the [[Core (microarchitecture)|Core microarchitecture]] and is thus clocked much lower than the Cedar Mill Celerons, but still outperforms them. It is based on the 65 nm [[Conroe (microprocessor)#Conroe-L|Conroe-L]] core,<ref>{{cite news| last=Huynh| first=Anh| title=Intel "Conroe-L" Details Unveiled| url=http://www.dailytech.com/article.aspx?newsid=4252| work=[[DailyTech]]| date=September 20, 2006| access-date=September 23, 2006| url-status=dead| archive-url=https://web.archive.org/web/20120306021304/http://www.dailytech.com/article.aspx?newsid=4252| archive-date=March 6, 2012| df=dmy-all}}</ref> and uses a 400-series model number sequence.<ref>{{cite news|url=http://www.vr-zone.com/?i=4657|title=Intel Adds Cheapest Celeron 420 In June|last=Visionary|date=February 13, 2007|work=VR-Zone|access-date=December 20, 2019|url-status=dead|archive-url=https://web.archive.org/web/20070303210711/http://www.vr-zone.com/?i=4657|archive-date=March 3, 2007}}</ref> The FSB was increased to 800 MT/s from 533 MT/s in this generation, and the TDP was decreased from 65 W to 35 W. As is traditional with Celerons, it does not have Intel [[X86 virtualization|VT-x]] instruction support or [[SpeedStep]] (although Enhanced Halt State is enabled, allowing the Celerons to lower the multiplier to 6× and decrease core voltage while idle). All Conroe-L models are single-core processors for the value segment of the market, much like the AMD K8-based [[Sempron]]. The product line was launched on June 5, 2007.<ref>{{cite news | url=http://www.heise.de/newsticker/meldung/90628 | title=Pentium Dual-Core E1000, Celeron 400, P35 und G33 starten offiziell | language=de | work=[[Heinz Heise|Heise News Ticker]] | date=June 5, 2007 | access-date=June 13, 2007}}</ref> On October 21, 2007, Intel presented a new processor for its Intel Essential Series. The full name of the processor is Celeron 220 and is soldered on the D201GLY2 motherboard. With 1.2 GHz and a 512 KB L2 cache it has a TDP of 19 W and can be cooled passively. The Celeron 220 is the successor of the Celeron 215 which is based on a Yonah core and used on the D201GLY motherboard. This processor is exclusively used on the mini-ITX boards targeted to the sub-value market segment. ==== Allendale {{Anchor|Allendale-512|Celeron Dual-Core}} ==== {{Main|Conroe (microprocessor)#Allendale}} Intel launched the dual core Celeron E1xxx processor line on January 20, 2008, based on the Allendale core. The CPU has 800 MT/s FSB, 65 W TDP and uses 512 KB of the chip's 2 MB L2 cache, significantly limiting performance for uses such as gaming. New features to the Celeron family included full enhanced halt state and enhanced Intel [[SpeedStep]] technology. Clock rates range from 1.6 GHz to 2.4 GHz. It is compatible with other Allendale-based CPUs such as the Core 2 Duo E4xxx and Pentium Dual-Core E2xxx.<ref>{{cite news| url=http://www.xbitlabs.com/news/cpu/display/20071011171900.html| title=Intel Preps Dual-Core Celeron Processors| date=October 11, 2007| access-date=November 12, 2007| url-status=dead| archive-url=https://web.archive.org/web/20071104025126/http://www.xbitlabs.com/news/cpu/display/20071011171900.html| archive-date=November 4, 2007| df=dmy-all}}</ref> ==== Wolfdale-3M ==== {{Main|Wolfdale (microprocessor)#Wolfdale-3M}} The Celeron E3000 series, starting with E3200 and E3300, was released in August 2009, featuring the Wolfdale-3M core used in [[Pentium Dual-Core]] E5000, Pentium E6000 and [[Core 2]] Duo E7000 series. The main difference to Allendale-based Celeron processors is the support for [[Intel VT-x]] and increased performance due to the double L2 Cache of 1 MB. === Nehalem-based Celerons === {{Main|List of Intel Celeron microprocessors#Nehalem based Celerons|List of Intel Celeron microprocessors#Nehalem based Celerons 3}} ==== Clarkdale ==== {{Main|Clarkdale (microprocessor)}} With the introduction of the Desktop Core i3 and Core i5 processor code named ''Clarkdale'' in January 2010, Intel also added a new Celeron line, starting with the Celeron G1101. This is the first Celeron to come with on-chip [[PCI Express]] and integrated graphics. Despite using the same Clarkdale chip as the Core i5-6xx line, it does not support [[Intel Turbo Boost|Turbo Boost]], [[HyperThreading]], [[Intel VT-d|VT-d]], [[Simultaneous multithreading|SMT]], [[Trusted Execution Technology]] or [[AES instruction set|AES new instructions]], and it comes with only 2 MB of third-level cache enabled.<ref>{{cite web|url=http://ark.intel.com/Product.aspx?id=43523&code=g1101|title=ARK – Intel® Celeron® Processor G1101 (2M Cache, 2.26 GHz)|work=Intel® ARK (Product Specs)}}</ref> ==== Jasper Forest ==== {{Main|Jasper Forest (microprocessor)}} The Celeron P1053 is an embedded processor for [[Socket 1366]] from the ''Jasper Forest'' family. All other members of this family are known as Xeon C35xx or C55xx. The Jasper Forest chip is closely related to [[Lynnfield (microprocessor)|Lynnfield]] and contains four cores, 8 MB of L3 cache and a QPI interface, but most of these are disabled in the Celeron version, leaving a single core with 2 MB of L3 cache. === Sandy Bridge-based desktop Celerons === [[File:Celeron G530 2.4GHz.jpg|thumb|right|200px|Celeron G530 2.4 GHz "Sandy Bridge"]] {{Main|List of Intel Celeron microprocessors#Sandy Bridge based Celerons}} The Sandy Bridge-based Celeron processors were released in 2011. They are [[LGA 1155]] processors (available in single- and dual-core versions) with integrated Intel HD Graphics GPU and containing up to 2 MB of L3 cache. Turbo-Boost, AVX and AES-NI have been disabled. Hyper-Threading is available on some single-core models, namely G460, G465 and G470. === Ivy Bridge-based desktop Celerons === {{Main|List of Intel Celeron microprocessors#.22Ivy_Bridge.22_.2822_nm.29}} All Celerons of this generation belong in the G16xx series. They give some boost in performance over Sandy Bridge-based Celerons due to a 22 nm die shrink, as well as some other minor improvements. === Haswell-based desktop Celerons === {{Main|Haswell (microarchitecture)}} === Skylake-based desktop Celerons === All Celerons of this generation added [[AES-NI]] and [[RDRAND]] instruction set. === Kaby Lake-based desktop Celerons === {{Main|Kaby Lake}} === Coffee Lake-based desktop Celerons === {{Main|Coffee Lake}} === Comet Lake-based desktop Celerons === {{Main|Comet Lake}} === Alder Lake-based desktop Celerons === {{Main|Alder Lake}}
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