Editing Chips and Technologies (section)

== Motherboard chips and chipsets ==
{{see also|NEAT chipset}}
* 82C100 - IBM PS/2 Model 30 and Super XT Computer Chip<ref>{{cite book | title=82C100 IBM PS/2 Model 30 and Super XT Compatible Chip | publisher=Chips and Technologies}}</ref> - Released in 1987,<ref>{{cite news
  | title = Firm Says System Logic Chip Will Speed PS/2 Model 30 Cloning
  | newspaper = InfoWorld
  | date = 1987-07-27
  | page = 26
  | url = https://books.google.com/books?id=6DsEAAAAMBAJ&pg=PA26
}}</ref> compatible with [[8086]], 80C86, [[NEC V30|V30]], [[8088]], 80C88, [[NEC V20|V20]] CPUs. Compatible with all [[PC/XT]] functional units: [[Intel 8284|8284]], [[Intel 8288|8288]], [[Intel 8237|8237]], [[Intel 8259|8259]], [[Intel 8254|8254]], [[Intel 8255|8255]], [[DRAM]] controller, [[Static random access memory|SRAM]] controller, Keyboard controller, Parity Generation and Configuration registers.<ref name=Tooley>{{cite book|title=PC Based Instrumentation and Control|author=Michael H. Tooley|pages=32|publisher=Elsevier|date=2005 |isbn=9780750647168}}</ref> Additionally features [[Expanded memory|EMS]] control, dual clock and power management. It supports up to 2.5 MB RAM.
* 82C206 chip, introduced by C&amp;T in 1986 and the core of the NEAT (New Enhanced AT) chipset.  This chip, like its predecessor the 82C100, provided equivalent functionality to the TTL chips on the [[IBM PC/AT|PC/AT]]'s mainboard, namely: the [[Intel 82284|82284]] clock generator, the [[Intel 82288|82288]] bus controller, the 8254 Programmable Interval Timer, the two 8259 Programmable Interrupt Controllers, the two 8237 DMA controllers, the [[MC146818]] [[Nonvolatile BIOS memory|NVRAM]]/[[real-time clock|RTC]] chip.<ref name=Mueller>{{cite book|title=Upgrading and Repairing PCs|author=Scott Mueller|pages=[https://archive.org/details/upgradingrepair100muel/page/230 230]|publisher=Que Publishing|date=2003|isbn=9780789729743|url-access=registration|url=https://archive.org/details/upgradingrepair100muel/page/230}}</ref>
* 82C235 - Single Chip AT (SCAT)<ref>{{cite book | title=82C235 Single Chip AT | publisher=Chips and Technologies}}</ref> - Released in 1989,<ref>{{cite news
  | title = Chip Makes Cheaper AT Clones possible
  | newspaper = InfoWorld
  | date = 1989-10-09
  | page = 1
  | url = https://books.google.com/books?id=pjAEAAAAMBAJ&pg=PA1
}}</ref> compatible with [[PC/AT]]. Supported LIM EMS 4.0, up to 16 MB memory and Shadow RAM.
* 82C351, 82C355, 82C356 / CS82310 (PEAK DM) - A three chip successor to NEAT for 32-bit 386DX CPUs. The PEAK DM/386 chipset supports up to 128MB of RAM in eight banks (32MB in two banks most commonly implemented), and up to 256KB of direct-mapped L2 cache.
* 82C836 - Single Chip 386sx AT (SCATsx)<ref>{{cite book | title=82C836 Single Chip 386sx AT | publisher=Chips and Technologies}}</ref> - Compatible with PC/AT (bus), supported all the features of SCAT, added support for the [[Intel 386#i386SX|i386SX]] processor and [[Intel 80387SX|i387SX]] math coprocessor, and optional external L2 cache.