Editing Chipset (section)

==Move toward processor integration in PCs==
[[File:Intel@10nm@CannonLake@PalmCoveCores - GT2-Gen10 IGP RadeonRX540@Core i3-8121U@NUC8I3CYSM DSCx08 poly@5xExt.jpg|thumb|Intel Cannon Lake Platform Controller Hub (PCH) die]]
Traditionally in x86 computers, the processor's primary connection to the rest of the machine was through the motherboard chipset's northbridge. The northbridge was directly responsible for communications with high-speed devices (system memory and primary expansion buses, such as PCIe, AGP, and PCI cards, being common examples) and conversely any system communication back to the processor. This connection between the processor and northbridge is commonly designated the [[front-side bus]] (FSB). Requests to resources not directly controlled by the northbridge were offloaded to the southbridge, with the northbridge being an intermediary between the processor and the southbridge. The southbridge handled "everything else", generally lower-speed peripherals and board functions (the largest being hard disk and storage connectivity) such as USB, parallel and serial communications. In 1990s and early 2000s, the interface between a northbridge and southbridge was the PCI bus.<ref>{{cite web |last1=Schmid |first1=Patrick |title=Chipset Basics: Meaning And Functions |url=https://www.tomshardware.com/reviews/full-power,490-2.html |website=[[Tom's Hardware]] |date=16 July 2002 |publisher=Purch |access-date=14 June 2018}}</ref>

Before 2003, any interaction between a CPU and main memory or an expansion device such as a graphics card(s)&nbsp;— whether [[Accelerated Graphics Port|AGP]], PCI or integrated into the motherboard&nbsp;— was directly controlled by the northbridge IC on behalf of the processor. This made processor performance highly dependent on the system chipset, especially the northbridge's memory performance and ability to shuttle this information back to the processor. In 2003, however, AMD's introduction of the [[Athlon 64]] series of processors<ref name="release">{{cite web |url=https://techreport.com/review/5683/amds-athlon-64-processor/ |title=AMD's Athlon 64 processor |first=Scott |last=Wasson |date=23 September 2003 |website=[[The Tech Report]] |access-date=5 December 2022}}</ref> changed this. The Athlon&nbsp;64 marked the introduction of an integrated memory controller being incorporated into the processor itself thus allowing the processor to directly access and handle memory, negating the need for a traditional northbridge to do so. Intel followed suit in 2008 with the release of its [[Core i]] series CPUs and the [[Intel X58|X58]] platform.

In newer processors integration has further increased, primarily through the inclusion of the system's primary PCIe controller and integrated graphics directly on the CPU itself. As fewer functions are left un-handled by the processor, chipset vendors have condensed the remaining northbridge and southbridge functions into a single chip. Intel's version of this is the "[[Platform Controller Hub]]" (PCH) while AMD's version was called [[Fusion Controller Hub]] (FCH). The PCH is still called a chipset.<ref>{{cite web | url=https://www.tomshardware.com/pc-components/motherboards/msi-z790-motherboards-reportedly-failing-with-cracked-pch-chipset-a-manufacturing-error-may-have-affected-a-few-hundred-units | title=MSI Z790 motherboards reportedly failing with cracked PCH chipset — a manufacturing error may have affected a few hundred units (Updated) | date=2 April 2024 }}</ref> This is an enhanced southbridge for the remaining peripherals—as traditional northbridge duties, such as memory controller, expansion bus (PCIe) interface and even on-board video controller, are integrated into the CPU die itself (the chipset often contains secondary PCIe connections though). However, the Platform Controller Hub was also integrated into the processor package as a second die for mobile variants of the [[Skylake (microarchitecture)|Skylake]] processors.<ref>{{cite web |url=https://www.anandtech.com/show/7047/the-haswell-ultrabook-review-core-i74500u-tested/2 |title=The Haswell Ultrabook Review: Core i7-4500U Tested |first=Anand Lal |last=Shimpi |author-link=Anand Lal Shimpi |date=9 June 2013 |website=[[AnandTech]] |access-date=5 December 2022}}</ref> 

AMD's FCH has been discontinued since the release of the Carrizo series of CPUs as it has been integrated into the same die as the rest of the CPU.<ref>{{cite web | url=https://www.anandtech.com/show/8995/amd-at-isscc-2015-carrizo-and-excavator-details | title=AMD at ISSCC 2015: Carrizo and Excavator Details }}</ref> However, since the release of the Zen architecture, there's still a component called a chipset which only handles relatively low speed I/O such as USB and SATA ports and connects to the CPU with a PCIe connection. In these systems all PCIe connections are routed directly to the CPU.<ref>{{cite web | url=https://www.anandtech.com/show/17585/amd-zen-4-ryzen-9-7950x-and-ryzen-5-7600x-review-retaking-the-high-end/4 | title=AMD Zen 4 Ryzen 9 7950X and Ryzen 5 7600X Review: Retaking the High-End }}</ref> The UMI interface previously used by AMD for communicating with the FCH is replaced with a PCIe connection. Technically the processor can operate without a chipset; it only continues to be present for interfacing with low speed I/O.<ref>{{cite web | url=https://www.anandtech.com/show/11170/the-amd-zen-and-ryzen-7-review-a-deep-dive-on-1800x-1700x-and-1700/13 | title=The AMD Zen and Ryzen 7 Review: A Deep Dive on 1800X, 1700X and 1700 }}</ref> AMD server CPUs adopt a self contained [[system on chip]] design instead which doesn't require a chipset.<ref>{{Cite web |title=4th Gen AMD EPYC Processor Architecture |url=https://www.amd.com/content/dam/amd/en/documents/products/epyc/4th-gen-amd-epyc-processor-architecture-whitepaper.pdf |access-date=3 November 2024 |website=AMD}}</ref><ref>{{Cite web |last=Kennedy |first=Patrick |date=2019-04-08 |title=Supermicro M11SDV-4C-LN4F Review mITX AMD EPYC 3151 Platform |url=https://www.servethehome.com/supermicro-m11sdv-4c-ln4f-review-mitx-amd-epyc-3151-platform/4/ |access-date=2024-08-18 |website=ServeTheHome |language=en-US}}</ref><ref>{{Cite web |last=Cutress |first=Andrei Frumusanu, Dr Ian |title=AMD 3rd Gen EPYC Milan Review: A Peak vs Per Core Performance Balance |url=https://www.anandtech.com/show/16529/amd-epyc-milan-review |access-date=2024-08-18 |website=www.anandtech.com}}</ref>

The northbridge to southbridge interconnect interfaces used now are [[Direct Media Interface|DMI]] ([[Intel]]) and [[UMI AMD|UMI]] ([[AMD]]). These can also be used for connecting from a processor to a chipset.