Editing Commodore 1571 (section)

== Technical design ==
The drive detects the motor speed and generates an internal data sampling [[clock signal]] that matches with the motor speed.<ref>{{Cite FTP |title=20 Pin Gate array (continued)
|publication-date=October 1986
|access-date=27 April 2016
|server=www.zimmers.net
|url=ftp://www.zimmers.net/pub/cbm/schematics/drives/new/1571/manual/05.html}}</ref>

The 1571 uses a saddle canceler when reading the data stream. A correction signal is generated when the raw data pattern on the disk consists of two consecutive zeros. With the [[Group coded recording|GCR]] recording format a problem occurs in the read signal waveform. The worst case pattern 1001 may cause a saddle condition where a false data bit may occur. The original 1541 drives uses a one-shot to correct the condition. The 1571 uses a gate array to correct this digitally.<ref>{{Cite FTP |title=20 Pin Gate array 1541B and 1571
|publication-date=October 1986
|access-date=27 April 2016
|server=www.zimmers.net
|url=ftp://www.zimmers.net/pub/cbm/schematics/drives/new/1571/manual/04.html}}</ref>

The drive uses the [[MOS Technology 6502|MOS 6502]] CPU, [[Western Digital FD1771|WD1770]] or WD1772 floppy controller, 2x [[MOS Technology 6522]] I/O controllers and 1x [[MOS Technology 6526]].<!--de:Commodore 128 article says so-->