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Connection Machine
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==Designs== {| class="wikitable mw-collapsible" ! colspan="15" |Thinking Machines '''Connection Machine models''' |- ! rowspan="2" | ! rowspan="5" | !1984 !1985 !1986 !1987 !1988 !1989 !1990 ! colspan="3" |1991 !1992 !1993 !1994 |- ! colspan="8" |Custom architecture ! rowspan="4" style="width:3px"; | ! colspan="4" | RISC-based ([[SPARC]]) |- |Entry | colspan="4" {{N/a}} | colspan="4" |CM-2a | colspan="4" {{N/a}} |- |Mainstream | {{N/a}} | colspan="2" |CM-1 | colspan="3" |CM-2 | colspan="2" {{N/a}} | colspan="2" rowspan="2" |CM-5 | colspan="2" rowspan="2" |CM-5E |- |Hi-end | colspan="4" {{N/a}} | colspan="4" |CM-200 |- ! colspan="15" | expansions |- |Storage ! | colspan="3" {{N/a}} | colspan="7" |[[DataVault]] | colspan="3" {{N/a}} |} [[File:Thinking machines cm2.jpg|thumb|300px|[[Thinking Machines Corporation|Thinking Machines]] CM-2 at the [[Computer History Museum]] in Mountain View, California. One of the face plates has been partly removed to show the circuit boards inside.]] Each CM-1 microprocessor has its own 4 [[kilobit]]s of [[random-access memory]] (RAM), and the [[Hypercube internetwork topology|hypercube]]-based array of them was designed to perform the same operation on multiple data points simultaneously, i.e., to execute tasks in single instruction, multiple data ([[Single instruction, multiple data|SIMD]]) fashion. The CM-1, depending on the configuration, has as many as 65,536 individual processors, each extremely simple, processing [[1-bit architecture|one bit]] at a time. CM-1 and its successor ''CM-2'' take the form of a [[cube]] 1.5 meters on a side, divided equally into eight smaller cubes. Each subcube contains 16 [[printed circuit board]]s and a main processor called a sequencer. Each circuit board contains 32 chips. Each chip contains a [[Router (computing)|router]], 16 processors, and 16 RAMs. The CM-1 as a whole has a 12-dimensional [[hypercube]]-based [[routing]] network (connecting the 2<sup>12</sup> chips), a main RAM, and an [[Channel I/O|input-output processor (a channel controller)]]. Each router contains five buffers to store the data being transmitted when a clear channel is not available. The engineers had originally calculated that seven buffers per chip would be needed, but this made the chip slightly too large to build. [[Nobel Prize]]-winning physicist [[Richard Feynman]] had previously calculated that five buffers would be enough, using a differential equation involving the average number of 1 bits in an address. They resubmitted the design of the chip with only five buffers, and when they put the machine together, it worked fine. Each chip is connected to a switching device called a nexus. The CM-1 uses [[Logarithm#Feynman's algorithm|Feynman's algorithm]] for computing logarithms that he had developed at [[Los Alamos National Laboratory]] for the [[Manhattan Project]]. It is well suited to the CM-1, using as it did, only shifting and adding, with a small table shared by all the processors. Feynman also discovered that the CM-1 would compute the Feynman diagrams for [[quantum chromodynamics]] (QCD) calculations faster than an expensive special-purpose machine developed at Caltech.<ref>{{cite journal |author-last=Hillis |author-first=W. Daniel |url=http://www.kurzweilai.net/articles/art0504.html?printable=1 |title=Richard Feynman and The Connection Machine |journal=[[Physics Today]] |volume=42 |issue=2 |publisher=Institute of Physics |date=1989b |pages=78β83 |doi=10.1063/1.881196 |bibcode=1989PhT....42b..78H |url-status=dead |archive-url=https://web.archive.org/web/20090728072503/http://www.kurzweilai.net/articles/art0504.html?printable=1 |archive-date=28 July 2009 |df=dmy-all |url-access=subscription }}</ref><ref>{{harvnb|Hillis|1989a}} - Text of Daniel Hillis' Physics Today article on Feynman and the Connection machine; also a video of Hillis *How I met Feynman *Feynman's last days.</ref> To improve its commercial viability, TMC launched the CM-2 in 1987, adding [[Weitek]] 3132 [[floating-point]] numeric [[coprocessor]]s and more RAM to the system. Thirty-two of the original one-bit processors shared each numeric processor. The CM-2 can be configured with up to 512 MB of RAM, and a redundant array of independent disks ([[RAID]]) [[hard disk]] system, called a [[DataVault]], of up to 25 GB. Two later variants of the CM-2 were also produced, the smaller ''CM-2a'' with either 4096 or 8192 single-bit processors, and the faster ''CM-200''. [[File:Frostburg (CM-5) - National Cryptologic Museum - DSC07914.JPG|thumbnail|200px|right|The light panels of [[FROSTBURG]], a CM-5, on display at the [[National Cryptologic Museum]]. The panels were used to check the usage of the processing nodes, and to run diagnostics.]] Due to its origins in AI research, the software for the CM-1/2/200 single-bit processor was influenced by the [[Lisp (programming language)|Lisp]] programming language and a version of [[Common Lisp]], [[*Lisp]] (spoken: ''Star-Lisp''), was implemented on the CM-1. Other early languages included [[Karl Sims]]' IK and Cliff Lasser's URDU. Much system utility software for the CM-1/2 was written in *Lisp. Many applications for the CM-2, however, were written in [[C*]], a data-parallel superset of [[ANSI C]]. With the ''CM-5'', announced in 1991, TMC switched from the CM-2's hypercubic architecture of simple processors to a new and different multiple instruction, multiple data ([[Multiple instruction, multiple data|MIMD]]) architecture based on a [[fat tree]] network of [[reduced instruction set computing]] (RISC) [[SPARC]] processors. To make programming easier, it was made to simulate a [[Single instruction, multiple data|SIMD]] design. The later ''CM-5E'' replaces the SPARC processors with faster SuperSPARCs. A CM-5 was the fastest computer in the world in 1993 according to the [[TOP500]] list, running 1024 cores with Rpeak of 131.0 G[[FLOPS]], and for several years many of the top 10 fastest computers were CM-5s.<ref>{{cite web |title=November 1993 |url=http://www.top500.org/lists/1993/11/ |website=www.top500.org |access-date=2015-01-16}}</ref>
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