Editing Cray-3 (section)

===Background===
Seymour Cray began the design of the Cray-3 in 1985, as soon as the [[Cray-2]] reached production.{{sfn|Trew|2012|p=245}} Cray generally set himself the goal of producing new machines with ten times the performance of the previous models. Although the machines did not always meet this goal, this was a useful technique in defining the project and clarifying what sort of process improvements would be needed to meet it.{{sfn|MacKenzie|1998|p=141}} For the Cray-3, he decided to set an even higher performance improvement goal, an increase of 12x over the Cray-2.{{sfn|MacKenzie|1998|p=153}}

Cray had always attacked the problem of increased speed with three simultaneous advances; more [[execution unit]]s to give the system higher [[Parallel computing|parallelism]], tighter packaging to decrease signal delays, and faster components to allow for a higher clock speed. Of the three, Cray was normally least aggressive on the last; his designs tended to use components that were already in widespread use, as opposed to leading-edge designs.{{sfn|MacKenzie|1998|p=141}}

For the Cray-2, he introduced a novel 3D-packaging system for its [[integrated circuit]]s to allow higher densities,{{sfn|Readings|2000|p=10}} and it appeared that there was some room for improvement in this process. For the new design, he stated that all wires would be limited to a maximum length of {{convert|1|foot}}. This would demand the processor be able to fit into a {{convert|1|cuft}} block, about {{frac|3}} that of the Cray-2 CPU. This would not only increase performance but make the system 27 times smaller.{{sfn|Trew|2012|p=246}}

For a 12x performance increase, the packaging alone would not be enough, the circuits on the chips themselves would also have to speed up. The Cray-2 appeared to be pushing the limits of the speed of [[silicon]]-based [[transistor]]s at 4.1&nbsp;ns (244&nbsp;MHz), and it did not appear that anything more than another 2x would be possible. If the goal of 12x was to be met, more radical changes would be needed, and a "high tech" approach would have to be used.{{sfn|MacKenzie|1998|pp=153–154}}

Cray had intended to use [[gallium arsenide]] circuitry in the Cray-2, which would not only offer much higher switching speeds but also used less energy and thus ran cooler as well. At the time the Cray-2 was being designed, the state of GaAs manufacturing simply was not up to the task of supplying a supercomputer.{{sfn|Readings|2000|p=9}} By the mid-1980s, things had changed and Cray decided it was the only way forward.{{sfn|MacKenzie|1998|p=154}} Given a lack of investment on the part of large chip makers, Cray decided to invest in a GaAs chipmaking startup, GigaBit Logic, and use them as an internal supplier.<ref>{{cite news |first=James |last=Peltz |url=https://www.latimes.com/archives/la-xpm-1990-01-23-fi-494-story.html |title=GigaBit Logic Negotiating Sale With Cray Computers |newspaper=Los Angeles Times |date=23 January 1990}}</ref>

Describing the system in November 1988, Cray stated that the 12 times performance increase would be made up of a three times increase due to GaAs circuits, and four times due to the use of more processors. One of the problems with the Cray-2 had been poor multiprocessing performance due to limited [[Bandwidth (computing)|bandwidth]] between the processors, and to address this the Cray-3 would adopt the much faster architecture used in the [[Cray Y-MP]]. This would provide a design performance of 8000 [[Million instructions per second|MIPS]], or 16 [[FLOPS|GFLOPS]].{{sfn|Trew|2012|p=246}}