Editing Cyrix (section)

== Products ==
{{original research|section|date=February 2014}}

=== Cyrix FasMath coprocessors ===
[[Image:KL Cyrix FasMath CX83D87.jpg|thumb|right|150px|Cyrix FasMath]]

The first Cyrix product for the [[personal computer]] market was a [[x87]] compatible [[Floating point unit|FPU]] [[coprocessor]]. The Cyrix FasMath 83D87 and 83S87 were introduced in November 1989.<ref>{{Cite news|last=Copeland|first=Ron|date=27 November 1989|title=Intel Claims Coprocessors Aren't Fully Compatible|volume=11|pages=8|work=[[InfoWorld]]|issue=48|publisher=[[InfoWorld Media Group, Inc.]]|url=https://books.google.com/books?id=tzAEAAAAMBAJ&dq=Cyrix+FasMath+83D87&pg=PT7|access-date=17 February 2022|issn=0199-6649}}</ref> The 83D87 was pin compatible with the [[Intel 80387SX|Intel 80387]], while the 83S87 was pin compatible with the [[Intel 80387SX|80387SX]]. Both provided up to 50% more performance, and additionally they had lower power consumption when idle, due to a low power operation.<ref>{{Cite book|url=https://www.datasheetarchive.com/pdf/download.php?id=411f62a720dd26c6c0327041b3188f3238b653&type=O&term=Cyrix%2520FasMath|title=Cyrix FasMath™ 83D87 Processor|publisher=Cyrix|year=1990}}</ref> Upon release the 83S87 cost $506 for a 16-MHz version and $556 for a 20-MHz version.<ref>{{Cite news|last1=Dryden|first1=Patrick|last2=Marshall|first2=Martin|date=26 March 1990|title=Cyrix Low-Drain Coprocessors Promise Faster Calculations|volume=12|pages=21|work=[[InfoWorld]]|issue=13|publisher=[[InfoWorld Media Group, Inc.]]|url=https://books.google.com/books?id=1DsEAAAAMBAJ&dq=Cyrix+FasMath+83S87&pg=PT20|access-date=17 February 2022|issn=0199-6649}}</ref> The Cyrix FasMath 82S87, a [[Intel 80287|80287]]-compatible chip, was developed from the Cyrix 83D87 and has been available since 1991.

[[Image:KL Cyrix 486DRx2.jpg|thumb|right|150px|Cyrix Cx486DRx² microprocessor]]

=== 486 ===

Its early CPU products included the [[486SLC]] and [[486DLC]], released in 1992, which, despite their names, were pin-compatible with the 386SX and DX, respectively. While they added an on-chip L1 cache and the 486 instruction set, performance-wise, they were somewhere between the 386 and the [[Intel 80486|486]]. The chips were mostly used as upgrades by end users looking to improve performance of an aging 386 and especially by dealers, who by changing the CPU could turn slow-selling 386 boards into budget 486 boards. The chips were widely criticized in product reviews for not offering the performance suggested by their names, and for the confusion caused by their naming similarity with [[Intel]]'s SL line and [[IBM]]'s [[386SLC|SLC]] line of CPUs, neither of which was related to Cyrix's SLC. The chips did see use in very low-cost PC clones and in laptops.

Cyrix would later release the Cyrix 486SRX2 and 486DRX2, which were essentially clock-doubled versions of the SLC and DLC, marketed exclusively to consumers as 386-to-486 upgrades. Unlike the SLC/DLC, these chips contained internal cache coherency circuitry which made the chips compatible with older 386 motherboards that did not have extra circuitry or BIOS routines to keep the cache current.

Eventually, Cyrix was able to release the [[Cyrix Cx486#Cx486S|Cyrix Cx486S]] and later [[Cyrix Cx486#Cx486DX|Cyrix Cx486DX]] that was pin-compatible with its Intel 486 counterparts. However, the chips were later to market than [[Advanced Micro Devices|AMD]]'s 486s and benchmarked slightly slower than AMD and Intel counterparts, which relegated them to the budget and upgrade market. While AMD had been able to sell some of its 486s to large [[Original equipment manufacturer|OEM]]s, notably [[Acer (company)|Acer]] and [[Compaq]], Cyrix had not. The Cyrix chips did gain some following with upgraders, as their 50-, 66-, and 80&nbsp;MHz 486 CPUs ran at 5&nbsp;V, rather than the 3.3&nbsp;V used by AMD, making the Cyrix chips usable as upgrades in early 486 motherboards.

=== Cyrix 5x86 ===

In 1995, with its [[Pentium]] clone not yet ready to ship, Cyrix repeated its own history and released the [[Cyrix Cx5x86]] (M1sc), which plugged into a 3.3V 486 socket, ran at 80, 100, 120, or 133&nbsp;MHz, and yielded performance comparable to that of a Pentium running at 75&nbsp;MHz. Cyrix 5x86 (M1sc) was a cost-reduced version of the flagship 6x86 (M1). Like Intel's Pentium Overdrive, the Cyrix 5x86 used a 32-bit external data bus. 
While AMD's [[AMD 5x86|Am5x86]] was little more than a clock-quadrupled 486 with a new name, Cyrix's 5x86 implemented some Pentium-like features.

[[Image:Cyrix 6x86-P166.jpg|right|thumb|180px|Cyrix 6x86-P166]]

=== Cyrix 6x86 ===

Later in 1995, Cyrix released its best-known chip, the [[Cyrix 6x86]] (M1). This processor continued the Cyrix tradition of making faster replacements for Intel designed sockets. However, the 6x86 was the star performer in the range, giving a claimed performance boost over the Intel "equivalent". 6x86 processors were given names such as P166+ indicating a performance better than a Pentium 166&nbsp;MHz processor. In fact, the 6x86 processor was clocked at a significantly lower speed than the Pentium counterpart it outperformed. Initially, Cyrix tried to charge a premium for the Cyrix-claimed extra performance, but the 6x86's math coprocessor was not as fast as that in the Intel [[Intel P5|Pentium]]. The main difference was not one of actual computing performance on the coprocessor, but a lack of instruction pipelining. Due to the increasing popularity of first-person 3D games, Cyrix was forced to lower its prices. While the 6x86 quickly gained a following among computer enthusiasts and independent computer shops, unlike AMD, its chips had yet to be used by a major OEM customer. The game in question causing most problems for performance was [[Id Software]]'s ''[[Quake (video game)|Quake]]''. Unlike previous 3D games, ''Quake'' used the pipelined Pentium FPU to do [[Texture mapping#Perspective correctness|perspective correction]] calculations in the background while [[texture mapping]], effectively doing two tasks at once. This would not have been a big problem for the 6x86 if, by that time, ''Quake'' had a fallback to do perspective correction without the FPU as in, for example, the game ''[[Descent (1995 video game)|Descent]]''. However, id Software chose not to include this. ''Quake'' also lacked the option to disable perspective correction, thus eliminating that potential speed boost for FPU-weak CPUs. This potential speed boost would have benefited not just Cyrix's users, but also users of AMD's K5 and especially of the 486. ''Quake''{{-'}}s optimization for the Pentium went beyond FPU usage and catered to a number of other architectural quirks specific to the Pentium, further hindering performance of other CPUs even outside FPU operations. This bias in favor of the Pentium served to boost the popularity of Intel's Pentium CPUs amongst the computer game community.

=== Cyrix 6x86L and 6x86MX ===

The later 6x86L was a revised 6x86 that consumed less power, and the 6x86MX (M2) added [[MMX (instruction set)|MMX]] instructions and a larger L1 cache. The [[Cyrix MII]], based on the 6x86MX design, was little more than a name change intended to help the chip compete better with the [[Pentium II]].

[[Image:KL Cyrix MediaGXm PGA.jpg|thumb|right|180px|Cyrix MediaGX]]

=== Cyrix MediaGX ===

In 1996, Cyrix released the [[MediaGX]] CPU, which integrated all of the major discrete components of a PC, including sound and video, onto one chip. Initially based on the old 5x86 technology and running at 120 or 133&nbsp;MHz, its performance was widely criticized but its low price made it successful. The MediaGX led to Cyrix's first big win, with Compaq using it in its lowest-priced [[Presario]] 2100 and 2200 computers. This led to further MediaGX sales to [[Packard Bell]] and also seemed to give Cyrix legitimacy, with 6x86 sales to both Packard Bell and [[eMachines]] following.

Later versions of the MediaGX ran at speeds of up to 333&nbsp;MHz and added MMX support. A second chip was added to extend its video capabilities.

=== Cyrix Media GXi, Jedi, and Gobi Cayenne ===

Cyrix developed the Cayenne core as an evolution of the 6x86MX/MII processor, with dual issue FPU, support for 3DNow instructions and a 256&nbsp;KB, 8-way associative, on-die L2 cache. This core was intended to be used in multiple products, including a successor to the MediaGX chip, a product codenamed Jedi which was to be a Socket&nbsp;7 compatible processor which was later cancelled in favor of a Socket&nbsp;370 compatible processor codenamed Gobi.<ref>{{cite web |url= http://www.cpushack.com/2012/10/31/cyrix-joshua-processor-from-peppers-to-the-bible/ |title=Cyrix Joshua Processor: From Peppers to the Bible |work=CPUShack Museum |date=31 October 2012 |access-date=November 1, 2017}}</ref>{{clarify|date=May 2020|reason=Why are we citing a source about the Cyrix Joshua processor without our article ever mentioning the Cyrix Joshua processor?}}

The Media GXi implementation was released in February 1997; intended for the mobile computing market, it had clock speeds of 120&nbsp;Mhz to 180&nbsp;Mhz, and had integrated graphics and audio controllers, making it useful for compact [[notebook computer]]s.<ref name="TweakTown">{{cite web |title=VIA C3 (AKA Cyrix 3) |page=1 |author=<!--Staff writer(s); no by-line.--> |date=July 5, 2001 |work=TweakTown |url=https://www.tweaktown.com/reviews/22/via_c3_aka_cyrix_3/index.html |access-date=May 26, 2020 |archive-date=July 29, 2020 |archive-url=https://web.archive.org/web/20200729035127/https://www.tweaktown.com/reviews/22/via_c3_aka_cyrix_3/index.html |url-status=dead }}</ref> Later that year, Cyrix was acquired by [[National Semiconductor]].

=== Cyrix M3 Jalapeno ===

This was a completely new core with a dual issue FPU, register renaming and out-of-order execution based on an 11-stage pipeline and 8-way associative, 8-way interleaved fully pipelined 256K L2 cache operating at core frequency.

Jalapeño's new floating point unit had dual independent FPU/MMX units and included both a fully pipelined, independent x87 adder and x87 multiplier. The Jalapeño design facilitated close integration between the core and the advanced 3D graphics engine, which was one of the first graphics subsystems to utilize a dual-issue FPU. The dual FPUs supported execution of both MMX and 3DNow instructions.

Jalepeno had an on-die memory controller based on RAMBUS technology capable of 3.2&nbsp;GB/s to reduce memory latency and an integrated on-board 3D graphics which purportedly could process up to 3&nbsp;million polygons per second and 266&nbsp;million pixels per second based on a 233&nbsp;Mhz clock. The on-die graphics had access to the L2 cache of the CPU to store textures. The design's initial clock speed target was 600-800&nbsp;Mhz with headroom to scale to 1&nbsp;Ghz and beyond. It was due to begin production in Q4&nbsp;1999 and launch in the year 2000 on a 0.18&nbsp;micron process with a die size of 110–120&nbsp;mm<sup>2</sup>.<ref>{{cite web |url= https://www.edn.com/microprocessor-forum-cyrix-spices-up-pc-with-jalapeno/ |title=Microprocessor Forum: Cyrix spices up PC with Jalapeño |author=<!--Staff writer(s); no by-line.--> |work=[[EDN (magazine)|EDN]] |date=October 14, 1998 |access-date=May 26, 2020}}</ref><ref>{{cite web |url= http://www.cpushack.com/CIC/announce/1998/M3.annc.html |author=<!--Staff writer(s); no by-line.--> |title=Press Release: Cyrix Unveils Jalapeño Core Architecture – Next generation processor delivers cutting-edge performance, advances integrated platform strategy |publisher=Cyrix |date=October 13, 1998 |via=CPUShack Museum |access-date=May 26, 2020}}</ref>

It is unclear how advanced development on this core was when Cyrix was acquired from National Semiconductor by [[VIA Technologies]] and the project discontinued. VIA did, however, continue producing late-generation Cyrix chips under the name VIA Cyrix III (also known as Cyrix 3).<ref name="TweakTown" />

=== PR system ===

Because the 6x86 was more efficient on an [[Instructions per cycle|instructions-per-cycle]] basis than Intel's Pentium, and because Cyrix sometimes used a faster bus speed than either Intel or AMD, Cyrix and competitor AMD co-developed the controversial [[Performance Rating]] (PR) system in an effort to compare their products more favorably with Intel's. Since a 6x86 running at 133&nbsp;MHz generally benchmarked slightly faster than a Pentium running at 166&nbsp;MHz, the 133&nbsp;MHz 6x86 was marketed as the 6x86-P166+. Legal action from Intel, who objected to the use of the strings "P166" and "P200" in non-Pentium products, led to Cyrix adding the letter "R" to its names.

The PR nomenclature was controversial because while Cyrix's chips generally outperformed Intel's when running productivity applications, on a clock-for-clock basis its chips were slower for [[floating point]] operations, so the PR system performed more poorly when running the newest games. Additionally, since the 6x86's price encouraged its use in budget systems, performance could drop even further when compared with Pentium systems that were using faster hard drives, video cards, sound cards, and modems.

Although AMD also used the PR numbers for its early [[AMD K5|K5]] chips, it soon abandoned that nomenclature with the introduction of the [[AMD K6|K6]]. However, it would use a similar concept in marketing its later CPUs, starting again with the Athlon XP.